Multi-Trigger Gate Driver for Flyback Converter FET Control
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Solution Overview
Problem
Existing solutions for controlling the secondary switching FET in transformer coupled synchronous rectified flyback converters face challenges due to noisy voltage ringings, leading to false triggering and increased power loss, requiring complex user adjustments and additional discrete components.
Innovation Solution
A circuit with a multi-trigger gate driver and sense triggers for VSD, IDS, and Vsec, along with a latchable turn-off logic, ensures accurate switching of the secondary FET by sensing voltage and current crossings, reducing false triggering and power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a power diode is used for rectification in the secondary circuit, then the circuit structure is simple, but substantial power loss occurs due to forward voltage drop during high current conduction
Solution Approach 1:
The patent replaces the power diode with a secondary switching FET, changing the key parameter of forward voltage drop from 0.7-1.0V (diode) to 0.1-0.2V (FET), thereby vastly reducing power loss during high current conduction while maintaining circuit functionality
2Loss of energy
If the secondary FET is turned on hard to shunt the body diode, then power loss is reduced, but false triggering occurs due to noisy voltage ringings
Solution Approach 1:
The patent introduces an intermediary zero-crossing detection circuit that monitors the source-drain voltage of the secondary FET and generates precise turn-on/turn-off trigger signals, acting as a mediator between the noisy voltage ringings and the FET gate drive to eliminate false triggering while maintaining efficient conduction
Solution Approach 2:
The patent implements feedback through zero-crossing detection of the source-drain voltage, where the detected zero-crossing events are fed back to control the gate drive timing, ensuring the FET is turned on and off at the correct moments despite the presence of voltage ringings
3Reliability
If complex user adjustments and additional discrete components are added to prevent false triggering, then reliability improves, but device complexity increases
Solution Approach 1:
The patent merges the zero-crossing detection function, trigger signal generation, and FET gate drive control into an integrated control circuit, eliminating the need for separate discrete components and complex user adjustments while maintaining reliable operation against false triggering
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces false triggering and power loss by accurately controlling the secondary FET switching cycles, even in the presence of voltage ringings, without the need for complex user adjustments or additional discrete components.
Implementation Method 1
a primary circuit 10 and a secondary circuit 30 magnetically coupled through a coupling transformer 20 having a primary transformer coil (PTC) 11 and a secondary transformer coil (STC) 31
Implementation Method 2
a VSD sense trigger 102 with a digital trigger output signal VSD-trigger 106. The analog inputs 104a and 104b of the VSD sense trigger 102 are respectively coupled to the FETsc 52 source and drain terminals for sensing its VSD
Data Source
AI summary
A secondary FETsc control circuit is disclosed for controlling FETsc of transformer coupled synchronous rectified flyback converter (TCSC). The control circuit includes source-drain voltage VSD sense trigger with output VSD-trigger activated upon positive 0-crossing of VSD. Drain-source current IDS sense trigger with output IDS-trigger activated upon positive 0-crossing of IDS. Secondary coil voltage Vsec sense trigger with output Vsec-trigger activated upon sensing negative Vsec. A multi-trigger gate driver (MTGD) has trigger inputs coupled to VSD-trigger, IDS-trigger, Vsec-trigger and drive output driving the FETsc gate. The MTGD has logic states of state-I where FETsc is turned off and latched, state-II where FETsc is turned off but unlatched, state-III where FETsc is turned on but unlatched. The MTGD is configured to enter state-III upon VSD-trigger, enter state-I upon IDS-trigger and enter state-IT upon Vsec-trigger. The control circuit thus avoids false triggering of the FETsc by numerous undesirable Vsec ringings.