Adaptive Off Time Control for Flyback PFC Circuits
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Solution Overview
Problem
Flyback type PFC converter circuits exhibit lower power factor and higher total harmonic distortion (THD) compared to boost type PFC converter circuits, leading to reduced efficiency in power factor correction.
Innovation Solution
A zero current detector control circuit and voltage control circuit are implemented to control the off time of the power factor corrector integrated circuit, forcing the line current waveform to be closer to an ideal sinusoidal waveform by increasing the fall time of the trailing edge of the pulse applied to the zero current detector input, thereby reducing THD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a flyback type PFC converter circuit is used, then the circuit can produce output voltage both greater and less than input voltage, but the power factor is lower and total harmonic distortion is higher compared to boost type
Solution Approach 1:
The patent applies dynamic control by making the off-time of the electronic switch variable rather than fixed. The off-time is dynamically adjusted based on the instantaneous phase angle of the AC input voltage, using a control circuit that detects voltage phase and generates corresponding timing signals. This dynamic timing adjustment reshapes the current waveform to be more sinusoidal, reducing total harmonic distortion while maintaining the flyback converter's versatile output voltage capability.
2Adaptability or versatility
If a flyback type PFC converter circuit is used, then the circuit can produce output voltage both greater and less than input voltage, but the power factor is lower compared to boost type
Solution Approach 1:
The patent applies dynamic control by making the off-time of the electronic switch variable rather than fixed. The off-time is dynamically adjusted based on the instantaneous phase angle of the AC input voltage, using a control circuit that detects voltage phase and generates corresponding timing signals. This dynamic timing adjustment reshapes the current waveform to be more sinusoidal, reducing total harmonic distortion while maintaining the flyback converter's versatile output voltage capability.
3Device complexity
If conventional fixed off-time control is used in flyback PFC, then the circuit operation is simple, but the input current waveform has high distortion and poor power factor
Solution Approach 1:
The patent introduces an intermediary control circuit between the power factor corrector IC and the electronic switch. This intermediary circuit includes a phase detection input that monitors the AC input voltage phase angle and generates control signals that modulate the off-time of the switch. This intermediary layer adds minimal complexity while effectively shaping the current waveform to reduce distortion and improve power factor.
4Object-generated harmful factors
If the off time is increased to reduce current distortion, then the power factor improves, but the switching frequency varies with phase angle
Solution Approach 1:
The patent accepts and utilizes the dynamic nature of switching frequency as a feature rather than a bug. By deliberately varying the off-time based on phase angle, the system achieves better current waveform shaping and power factor improvement. The dynamic switching frequency is a direct result of the adaptive off-time control strategy that prioritizes power factor correction performance over frequency stability.
Data Source
AI summary
A zero current detector control circuit controls a voltage applied to a zero current detector (ZCD) input of a power factor corrector integrated circuit (PFC IC) that produces a driver output having an on time and an off time. The zero current detector control circuit includes a voltage detection input circuit coupled to a rectified AC input voltage. The detector control circuit generates a control voltage applied to a control terminal of an electronic switch. When the rectified AC input voltage has a phase angle in a first portion or in a last portion of a half-cycle, the electronic switch conducts to connect a capacitor to the ZCD input of the PFC IC. The capacitor causes the fall time of the trailing edge of a pulse applied to the ZCD input to increase, which causes the off time of the driver output of the PFC IC to increase.