Flyback PFC Multiplier Circuit for THD Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flyback type power factor correction (PFC) converter circuits suffer from reduced power factor and increased total harmonic distortion (THD) due to distorted line current waveforms, which are not sinusoidal and are out of phase with the input voltage, leading to lower efficiency compared to boost type PFC converters.
Innovation Solution
A multiplier circuit is introduced to alter the current waveform through the primary winding of the PFC circuit, forcing it to be closer to an ideal sinusoidal shape by switching between different operational modes based on the voltage across an energy storage device, thereby reducing THD and improving the power factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a flyback type PFC converter circuit is used, then the converter can produce output voltage both greater and less than input voltage, but the power factor is reduced and total harmonic distortion is increased
Solution Approach 1:
The patent applies dynamics by making the off-time of the switching element variable rather than fixed. The control circuit adjusts the off-time based on the instantaneous voltage across the energy storage device, allowing the switching parameters to adapt dynamically throughout each switching cycle. This dynamic adjustment compensates for the non-sinusoidal current waveform, reducing harmonic distortion while maintaining the flyback converter's versatile output voltage capability.
2Adaptability or versatility
If a flyback type PFC converter circuit is used, then the converter can produce output voltage both greater and less than input voltage, but the power factor is reduced
Solution Approach 1:
The patent implements feedback by using the voltage across the energy storage device as a sensing signal that feeds back to the control circuit. This feedback mechanism allows the control circuit to continuously monitor the instantaneous voltage and adjust the switching element's off-time accordingly, ensuring the input current remains in phase with the input voltage and improving the power factor while preserving the flyback topology's output voltage flexibility.
3Device complexity
If the off-time of the switching element is fixed, then the control is simplified, but the line current waveform becomes distorted and non-sinusoidal
Solution Approach 1:
The patent applies parameter changes by varying the off-time parameter of the switching element based on the instantaneous voltage conditions. Instead of using a fixed off-time, the control circuit dynamically changes the off-time parameter in response to the voltage across the energy storage device, thereby shaping the line current waveform to be more sinusoidal and in phase with the input voltage, reducing harmonic distortion.
4Power
If the line current waveform is forced to be sinusoidal and in phase with input voltage, then power factor improves, but additional control complexity is introduced
Solution Approach 1:
The patent uses the voltage across the energy storage device as an intermediary signal that mediates between the simple flyback switching operation and the desired sinusoidal current waveform. By using this naturally occurring voltage waveform as the basis for controlling the off-time, the circuit achieves power factor correction without requiring complex external multiplier circuits or additional sensing mechanisms, thus improving power factor while limiting the increase in overall system complexity.
Data Source
AI summary
A multiplier signal, and multiplier circuits and methods are provided to improve the total harmonic distortion (THD) and power factor (PF) for a flyback type power factor correction (PFC) circuit. The multiplier signal has a “pulled-up” waveshape that is configured to compensate for the “push-down” effect of varying off times of an electronic switch of the PFC on a line current of the PFC. The multiplier circuit is configured to reduce the multiplier signal during a first operational mode of the multiplier circuit and is further configured to maintain a typical multiplier signal during a second operational mode. The first operational mode occurs before a first phase angle and after a second phase angle during each half-cycle of a power source coupled to the PFC circuit. The second operational mode occurs between the first and second phase angles during each half-cycle.