Flying-Adder Fractional Clock Divider Without PLL Feedback
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Solution Overview
Problem
Conventional phase locked loop (PLL) based frequency division methods are inefficient in achieving fractional frequency division due to power and area costs, and introduce frequency inaccuracies due to feedback mechanisms, making them unsuitable for modern electronic systems requiring precise clock signal generation.
Innovation Solution
An open-loop fractional frequency division architecture using a flying-adder divider, which eliminates feedback loops and employs a first integer divider, a flying-adder synthesizer for fractional division, and a second integer divider for post-divider fractional recovery, allowing for direct and accurate frequency division without feedback-induced errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PLL based frequency division is used to achieve fractional frequency division, then frequency division capability is improved, but power consumption and area requirements increase
Solution Approach 1:
The frequency division function is segmented into two independent stages: first an integer divider stage that divides the input frequency by an integer N, then a fractional divider stage that performs fractional division by a ratio P/Q. This segmentation allows each stage to be optimized independently, reducing overall power consumption compared to a monolithic PLL approach while maintaining full frequency division capability.
Solution Approach 2:
The feedback mechanism is extracted and removed from the frequency division system. By eliminating the PLL feedback loop, the design achieves fractional frequency division through open-loop operation, significantly reducing power consumption and area requirements while avoiding feedback-induced frequency inaccuracies.
2Adaptability or versatility
If conventional PLL based frequency division is used to achieve fractional frequency division, then frequency division capability is improved, but implementation complexity increases
Solution Approach 1:
The complex fractional division function is segmented into simpler integer division and fractional division stages. The first stage uses a conventional integer divider with divide ratio N, and the second stage uses a fractional divider with ratio P/Q. This segmentation reduces implementation complexity by breaking down the challenging fractional division task into manageable, well-understood components.
Solution Approach 2:
The feedback control mechanism is extracted and removed from the system. By using open-loop operation instead of closed-loop PLL, the design eliminates complex feedback paths, phase detectors, and loop filters, significantly reducing implementation complexity while achieving the same frequency division functionality.
3Adaptability or versatility
If conventional PLL based frequency division is used, then fractional frequency division is achieved, but frequency accuracy deteriorates due to feedback mechanisms
Solution Approach 1:
The feedback mechanism is extracted and removed from the frequency division system. By operating in open-loop mode, the design eliminates feedback-induced frequency errors, phase noise, and jitter that plague PLL-based solutions. The fractional frequency division is achieved directly through the divider ratios without any feedback correction, resulting in superior frequency accuracy.
Solution Approach 2:
Instead of using feedback to correct frequency errors (the conventional PLL approach), the design inverts the approach by eliminating feedback entirely and achieving frequency accuracy through precise open-loop division ratios. The frequency accuracy is determined by the precision of the divider ratios P/Q and N rather than by feedback loop characteristics.
Data Source
AI summary
An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.