Flying-Capacitor Level Shifter for Symmetrical Fast Signal Translation
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Solution Overview
Problem
Conventional level shifters exhibit slow and asymmetrical propagation delays, leading to duty cycle distortion, which degrades the performance of integrated circuits operating across different voltage domains.
Innovation Solution
A capacitive level shifter employing a flying capacitor and a differential amplifier configuration with complementary transistors and a diode-mirrored load circuit, which maintains charge across the capacitor for indefinite logic states, enabling fast and symmetrical signal translation between voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional level shifter uses cross-coupled transistors to translate signals between voltage domains, then signal translation is achieved, but propagation delay becomes slow and asymmetrical
Solution Approach 1:
The patent uses a flying capacitor that dynamically switches between charging and discharging states based on the input signal logic level. The capacitor is charged to VDD when input is logic '1' and discharged to 0V when input is logic '0', enabling fast transitions that reduce propagation delay while maintaining accurate signal translation between voltage domains.
Solution Approach 2:
The patent changes the voltage parameter of the flying capacitor to encode the input signal logic level. By charging the capacitor to a high voltage state (VDD) for logic '1' and discharging to a low voltage state (0V) for logic '0', the system achieves fast switching with symmetrical propagation delays, resolving the contradiction between speed and translation accuracy.
2Ease of operation
If a conventional level shifter uses asymmetrical transistor switching, then signal translation occurs, but duty cycle distortion increases
Solution Approach 1:
The patent replaces the mechanical transistor switching mechanism with an electrical capacitor charging/discharging system. The flying capacitor is charged through a current source when input is logic '1' and discharged through a transistor when input is logic '0', creating symmetrical rise and fall times that eliminate duty cycle distortion while maintaining simple signal translation operation.
Solution Approach 2:
The patent implements periodic charging and discharging of the flying capacitor that corresponds to the input signal transitions. This periodic action ensures that each logic transition (0 to 1 or 1 to 0) produces symmetrical output waveforms with equal rise and fall times, thereby maintaining accurate duty cycle while simplifying the translation operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive level shifter achieves propagation delays of less than one nanosecond with negligible duty cycle distortion, significantly improving signal translation efficiency between voltage domains.
Implementation Method 1
establishing a charge across a capacitor based on a logic level of an input signal received by a circuit in the first voltage domain. The method includes maintaining the charge across the capacitor based on the logic level
Data Source
AI summary
A level shifter includes a flying capacitor having a first plate and a second plate. The level shifter includes a circuit coupled to the first plate and coupled to the second plate. The circuit is configured to receive a received signal having a logic state using a first voltage domain and configured to generate a symmetrical output signal having the logic state using a second voltage domain based on charge stored by the flying capacitor. The level shifter has a propagation delay from the received signal to the symmetrical output signal of less than one nanosecond with negligible duty cycle distortion.