Flying Capacitor Memory Driver for Voltage Stress Tolerance

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Solution Overview

Problem

Conventional memory driver circuits based on cross-coupled level shifter circuits face performance issues due to high threshold voltage of thick-oxide semiconductor devices, leading to increased power consumption and noise, which limits their ability to achieve competitive power, performance, and area (PPA) specifications.

Innovation Solution

The implementation of a memory driver circuit using a flying capacitor circuit, which includes a pair of thick-oxide and thin-oxide PMOS and NMOS transistors cross-coupled to protect thin-oxide transistors from voltage stress, allowing for level-shifting of input signals and reducing voltage across thin-oxide devices within their tolerance limits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cross-coupled level shifter circuits are used in memory driver circuits, then level shifting function is achieved, but power consumption increases and noise increases

Engineering Contradiction:
Improvelevel shifting functionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The circuit is divided into two distinct paths: a thick-oxide transistor path for voltage stress tolerance and a thin-oxide transistor path for low-power operation. This segmentation allows each path to be optimized for its specific function, resolving the contradiction between reliability and power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A flying capacitor is introduced as an intermediary element to transfer signals between the thick-oxide and thin-oxide transistor paths. This mediator enables the thick-oxide path to provide voltage stress tolerance while the thin-oxide path maintains low power consumption, as the capacitor isolates the two paths during signal transfer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If thick-oxide semiconductor devices are used for voltage stress tolerance, then reliability improves, but threshold voltage increases leading to higher power consumption

Engineering Contradiction:
Improvevoltage stress toleranceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The circuit segments transistor functions by oxide thickness, dedicating thick-oxide transistors to voltage stress tolerance in the level shifting path while using thin-oxide transistors for the output path where low power consumption is critical. This segmentation resolves the contradiction by assigning each transistor type to its optimal operational role.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the circuit use different oxide thicknesses based on local requirements: thick-oxide transistors are placed where voltage stress tolerance is needed (level shifting path), while thin-oxide transistors are placed where low power consumption is needed (output path). This local quality differentiation resolves the contradiction between voltage stress tolerance and power consumption.

Inventive Principle:
Principle #3Local quality

3Use of energy by moving object

If thin-oxide transistors are used to reduce power consumption, then power efficiency improves, but voltage stress tolerance decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidvoltage stress tolerance
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The circuit segments the transistor paths by oxide thickness, placing thin-oxide transistors in the output path for low power consumption while protecting them from voltage stress through the thick-oxide transistor path and flying capacitor isolation. This segmentation allows thin-oxide transistors to operate efficiently without suffering from voltage stress.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit provides beforehand protection to thin-oxide transistors by using thick-oxide transistors and a flying capacitor to isolate and protect the thin-oxide path from voltage stress before the stress can affect the thin-oxide devices. This prior cushioning enables thin-oxide transistors to operate at low power without suffering from voltage stress damage.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Reliability

If conventional level shifter circuits are used, then level shifting is achieved, but switching noise increases

Engineering Contradiction:
Improvelevel shifting functionVSAvoidswitching noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The circuit segments the switching operations between thick-oxide and thin-oxide transistor paths, with the flying capacitor isolating the noisy thick-oxide switching from the sensitive output path. This segmentation reduces switching noise by preventing noise propagation from the voltage stress tolerance path to the output path.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9754646B1Voltage stress tolerant high speed memory driver having flying capacitor circuit
Publication Date: 2017.09.05 CADENCE DESIGN SYST INC
  • US9754646B1 patent drawing
  • US9754646B1 patent drawing
  • US9754646B1 patent drawing

AI summary

Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.