Flying-Capacitor Totem-Pole Boost PFC for Zero-Crossing Distortion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power factor correction (PFC) converters in data centers face challenges in achieving high efficiency and power density due to limitations in switching frequency and the presence of zero-crossing distortions, especially at light loads.
Innovation Solution
A multi-level, bridgeless boost PFC device with a flying capacitor, totem-pole configuration is introduced, featuring a control circuit that reduces line current distortions by disabling switch conduction around zero-crossings and employing feedforward duty cycle control with mixed conduction modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If hard switching of totem-pole switches is used to achieve continuous conduction mode, then efficiency is improved, but switching frequency must be kept low which increases the volume of PFC choke and EMI filter
Solution Approach 1:
The patent segments the single-stage PFC converter into a two-stage architecture: a first PFC stage operating in CCM and a second PFC stage operating in DCM. This segmentation allows each stage to operate at optimized switching frequencies, with the first stage using lower frequency hard switching and the second stage using higher frequency soft switching, thereby reducing the overall volume of magnetic components while maintaining high efficiency.
Solution Approach 2:
The patent implements dynamic switching frequency adjustment where the switching frequency of the first PFC stage is modulated based on the instantaneous line voltage. During light load conditions, the frequency is reduced to minimize switching losses, while during heavy load conditions, the frequency is increased to maintain continuous conduction mode. This dynamic adjustment resolves the contradiction between maintaining CCM and reducing switching losses.
2Volume of stationary object
If switching frequency is increased to reduce the volume of PFC choke and EMI filter, then power density is improved, but switching losses increase which reduces efficiency
Solution Approach 1:
The patent divides the PFC function into two independent stages that can operate at different switching frequencies. The first stage operates at a lower frequency optimized for CCM operation with minimal switching losses, while the second stage operates at a higher frequency optimized for compact magnetic component sizes. This segmentation allows simultaneous optimization of both efficiency and power density without compromise.
Solution Approach 2:
The patent changes the operating parameters of the two stages differently: the first stage maintains low switching frequency and CCM operation for high efficiency, while the second stage uses high switching frequency and DCM operation for reduced component volume. This parameter differentiation resolves the contradiction by allowing each stage to optimize for its primary objective.
3Volume of stationary object
If multi-level FCML topology is used to increase switching frequency and reduce component size, then power density is improved, but zero-crossing distortion of line current increases especially at light loads
Solution Approach 1:
The patent segments the PFC operation into two stages where the first stage handles the bulk of the power conversion in CCM with minimal zero-crossing distortion, while the second stage in DCM handles the remaining power and naturally provides zero-crossing correction. This segmentation isolates the zero-crossing distortion issue to the second stage where it can be managed without affecting the overall power factor correction performance.
Solution Approach 2:
The patent converts the potentially harmful zero-crossing distortion generated by the multi-level FCML topology into a beneficial feature by operating the second PFC stage in DCM. The discontinuous conduction mode naturally allows the inductor current to reach zero at line voltage zero-crossings, which corrects the distortion and improves the overall power factor. Thus, what could be a harmful distortion is transformed into a corrective mechanism.
4Loss of energy
If totem-pole switches are operated in CCM to maintain continuous conduction, then efficiency is improved, but at light loads zero-crossing distortion increases due to discontinuous current operation
Solution Approach 1:
The patent segments the PFC function into two stages with different conduction modes: the first stage operates in CCM to maintain efficiency and minimize switching losses, while the second stage operates in DCM to provide natural zero-crossing current operation. This segmentation allows the system to simultaneously achieve low switching losses and reduced zero-crossing distortion by distributing these functions across the two stages.
Solution Approach 2:
The patent applies partial CCM operation in the first stage and partial DCM operation in the second stage, rather than requiring full CCM operation throughout. This partial application of conduction modes allows the system to achieve the benefits of both CCM (low switching losses) and DCM (natural zero-crossing current) without requiring either mode to operate at full capacity, thereby resolving the contradiction at light loads.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
In one embodiment, a multi-level, bridgeless boost power factor correction (PFC) device (50), comprising: a circuit (52) comprising an inductor (51), and at least a first pair and a second pair of switches and a capacitor (59) arranged in a flying capacitor, totem-pole configuration; and a control circuit (54) configured to drive the at least first and second pairs of switches in such a way as to reduce distortion in a line current, wherein for the first and second pairs of switches, the control circuit (54) is configured to: for a first half-line cycle, drive a first switch (53a, 55a) of each pair during an entire interval of the first half-line cycle and a second switch (53b, 55b) of each pair for less than the entire interval; and for a second half-line cycle, drive the first switch (53a, 55a) of each pair for less than an entire interval of the second half-line cycle and the second switch (53b, 55b) of each pair during an entire interval of the second half-line cycle.