3-Level Flying Capacitor PWM With Single-Carrier Phase Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-efficiency, high-power density power electronic converters face challenges with electromagnetic interference (EMI) and voltage ripple due to the use of wide-bandgap switches, particularly in three-level flying capacitor multi-level converters, where conventional modulation methods suffer from drift between phase-shifted carrier signals leading to unstable output voltage and increased complexity.
Innovation Solution
A single-carrier sensor-less pulse-width modulation method is proposed for three-level flying capacitor multi-level converters, using a single carrier signal to generate switching signals for pairs of wide-bandgap switches, reducing EMI and voltage ripple by eliminating drift and odd multiples of switching harmonic clusters, thereby simplifying the modulation process and improving output voltage spectrum.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional two-carrier PS-PWM method is used to generate switching signals, then switching signals can be generated for driving the various pair of switches, but drift or time lag between phase-shifted carrier signals occurs leading to increased voltage ripple and unbalanced flying capacitor voltage
Solution Approach 1:
The patent merges two separate carrier signal generators into a single carrier signal generator that produces both phase-shifted carrier signals simultaneously. This eliminates the drift and time lag issues between separate carriers by ensuring both carriers are generated from the same reference clock source, thereby maintaining stable output voltage and balanced flying capacitor voltage while still enabling switching signal generation for all switch pairs.
2Productivity
If high switching frequency is employed in WBG based 3L-FCM converter, then efficiency is improved, but the impact of drift or time lag between two phase-shifted carrier signals on voltage ripple and voltage balancing is exacerbated
Solution Approach 1:
The patent combines the carrier signal generation functions into a single integrated carrier signal generator that produces both phase-shifted carriers from one reference clock. This merging eliminates the frequency drift and time lag problems that become more severe at high switching frequencies, allowing the converter to operate at high frequencies with WBG devices while maintaining stable voltage ripple and voltage balancing performance.
3Loss of energy
If standard silicon-based IGBTs and MOSFETs are replaced with SiC and GaN switches, then switching loss is reduced and efficiency is improved, but electromagnetic interference increases significantly requiring enlarged EMI filter
Solution Approach 1:
The patent uses a merged single-carrier PWM approach that generates switching signals with reduced spectral content at odd harmonic frequencies. This modulation strategy, combined with the use of wide-bandgap devices, reduces electromagnetic interference by minimizing the high-frequency switching noise while maintaining the low switching loss benefits of SiC and GaN devices, thereby reducing the required EMI filter size.
4Ease of operation
If two separate carrier signal generators are used to generate phase-shifted carrier signals, then switching signals can be generated for each cell, but drift between carrier signals occurs leading to increased complexity and larger flying capacitor requirements
Solution Approach 1:
The patent merges the function of two separate carrier signal generators into a single carrier signal generator that produces both phase-shifted carrier signals from one reference clock source. This eliminates drift between carriers, simplifies the control system, and reduces the flying capacitor size requirements by maintaining precise voltage balancing, thereby reducing overall device complexity while still enabling independent control of each cell.
Data Source
AI summary
A three-level flying capacitor multi-level (3L-FCM) power converter is controlled by a switching signal generator having a reference signal for generating switching signals for driving a first pair S1, S1′ and a second pair S2, S2′ of switches. Circuitry generates, from the reference signal, a first modified reference signal defined as half of the sum of 1 and the reference signal. From the first modified reference signal a second modified reference signal is generated having a half-period phase shift from the first modified reference signal. A carrier signal having a constant frequency is generated and a first comparator and a second comparator compare the first and the second modified reference signals to the carrier signal to generate frequency signals for driving the first pair of switches S1, S1′, and the second pair of switches S2, S2′, respectively.