Flying Decoder Lines in Memory Devices

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Solution Overview

Problem

In memory devices, the large parasitic RC value in word line decoders leads to delays in providing WL decode signals, resulting in increased access time and setup time.

Innovation Solution

The implementation of M4 tracks in parallel with M2 tracks, with M4 tracks disposed vertically above M2 tracks, reduces parasitic resistance and optimizes space usage, thereby improving the RC delay and access times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional single-layer decoder lines are used, then the layout is simple, but the parasitic RC value is large causing delays

Engineering Contradiction:

Improvedecoder layout complexityVSAvoidaccess time and setup time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent transitions from a single-layer decoder line layout to a multi-layer metallization structure. Specifically, it uses a first metallization layer with decoder lines extending in a first direction, and a second metallization layer with decoder lines extending in a second direction perpendicular to the first direction. This dimensional change allows signal paths to be routed through multiple layers, reducing parasitic RC values and improving access time without significantly increasing layout complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If more metal tracks are added to reduce parasitic resistance, then the RC delay improves, but the area occupied increases

Engineering Contradiction:

ImproveRC delay performanceVSAvoidback-end area for metal lines

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of adding more metal tracks in the same plane which would increase area, the patent utilizes vertical stacking with multiple metallization layers. The first and second metallization layers are positioned at different heights, allowing decoder lines to be routed in three dimensions. This approach reduces parasitic resistance by providing additional parallel signal paths without proportionally increasing the planar area occupied by the decoder.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges the functionality of decoder lines from multiple metallization layers to work together as a unified signal transmission system. The first decoder lines in the first metallization layer and the second decoder lines in the second metallization layer are interconnected to form combined signal paths, effectively reducing parasitic resistance by distributing the electrical load across multiple parallel conductors in different layers.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250166680A1Memory devices with flying decorder lines and methods for operating the same

Publication Date: 2025.05.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a plurality of first decoder lines disposed in a first metallization layer and extending in a first direction. Each of the first decoder lines includes at least a first segment and a second segment operatively coupled to a plurality of first memory cells and a plurality of second memory cells, respectively. The first segment and second segment of each of the first decoder lines are arranged side-by-side along the first direction.