Fused-Multiply-Add System Asymmetric Parallel Paths
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Solution Overview
Problem
Conventional fused-multiply-add (FMA) systems fail to meet low latency and low power requirements of modern applications, leading to slower response times and increased power consumption.
Innovation Solution
A modified FMA system that performs asymmetrical additions in parallel paths, utilizing a multiplier, alignment shifter, adder, subtractor, leading zero counter, and multiplexer to reduce latency and power consumption, eliminating the need for a conditional complementor and minimizing subtractor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional FMA designs are used, then basic functionality is provided, but latency and power consumption requirements are not met
Solution Approach 1:
The FMA operation is segmented into two parallel asymmetric paths: one for addition (a*b + c) and one for subtraction (a*b - c). Each path has dedicated hardware (adder or subtractor) that operates independently and simultaneously, allowing the system to complete both operations in the same time frame, thereby reducing latency without proportionally increasing complexity
Solution Approach 2:
The system dynamically selects which path result to output based on the sign bit of operand c. The multiplexer dynamically switches between the adder output and subtractor output based on control signals, enabling adaptive operation that optimizes performance for different input conditions while maintaining low latency
2Use of energy by stationary object
If conventional FMA designs are used, then basic functionality is provided, but power consumption is reduced
Solution Approach 1:
The alignment shifter performs preliminary alignment of operand c with the product a*b before the addition or subtraction operation. This preliminary action ensures that the main arithmetic operations can proceed immediately without additional alignment steps, reducing overall operation time and enabling higher frequencies while keeping power consumption low through efficient timing
Solution Approach 2:
The system changes operational parameters by using asymmetric paths with different hardware configurations optimized for their specific functions. The adder and subtractor use different internal structures and timing parameters, allowing each to operate at optimal efficiency for its operation type, reducing overall power consumption while maintaining high productivity
3Speed
If parallel asymmetric paths are used, then latency is reduced, but hardware complexity increases
Solution Approach 1:
The multiplexer serves multiple functions: it selects between adder and subtractor outputs, routes results to the appropriate normalization stage, and works with the leading zero counters to determine final output formatting. This multi-functionality reduces the need for separate dedicated components, lowering overall hardware complexity while maintaining high operation speed
Solution Approach 2:
The design uses asymmetric paths where the adder and subtractor have different internal structures and timing characteristics optimized for their specific operations. This asymmetry allows each path to be minimized for its particular function rather than requiring a symmetric design that would be larger and slower, thus reducing latency without excessive complexity increase
Data Source
AI summary
A fused-multiply-add system is disclosed. The fused-multiply-add system includes a multiplier to multiply first and second operands and to provide at least one product. The fused-multiply-add system also includes an alignment shifter for aligning a third operand with the at least one product to provide an aligned third operand. The fused-multiply-add system also includes an adder and a subtractor coupled to the multiplier and the alignment shifter for performing two asymmetrical additions in parallel paths. The fused-multiply-add system also includes at least one leading zero counter for counting a number of leading zero bits provided by at least one of the adder and the subtractor to provide at least one normalization shift amount. Finally, the fused-multiply-add system includes a multiplexer coupled to the adder and the subtractor for providing an appropriate output based upon a sign bit.