Floating-Point Fused Multiply-Add With Conditional Normalization
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Solution Overview
Problem
Current graphics processing units (GPUs) face inefficiencies and high power consumption in performing floating point fused multiply-add (FMA) operations due to the varying cost of calculations based on the relative values of the operands, with multiplication being the most costly operation.
Innovation Solution
Optimizing FMA operations by bypassing usual normalization circuitry and applying bit adjustments to reduce operations, particularly when the addend's least significant bits overlap the most significant bits of the product, while maintaining compliance with the IEEE floating point standard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full normalization circuitry is used in FMA operations, then IEEE floating point standard compliance is ensured, but power consumption and processing time increase
Solution Approach 1:
The patent applies local quality by making the normalization process conditional rather than uniform. When the addend's least significant bits overlap with the product's most significant bits, full normalization is bypassed. This localized optimization reduces power consumption in specific cases while maintaining IEEE compliance through rounding adjustments, resolving the contradiction between reliability and energy efficiency.
Solution Approach 2:
The patent changes the normalization parameter from a fixed full normalization process to a conditional process that adjusts based on operand characteristics. By detecting bit overlap conditions and selectively applying normalization, the system achieves both IEEE compliance and reduced power consumption, effectively resolving the technical contradiction.
2Measurement precision
If full normalization is performed in FMA operations, then accuracy is maintained, but processing speed decreases
Solution Approach 1:
The patent implements preliminary action by detecting the bit overlap condition between the addend's least significant bits and the product's most significant bits before performing normalization. This pre-detection allows the system to bypass unnecessary full normalization steps when conditions permit, thereby maintaining accuracy while improving processing speed.
Solution Approach 2:
The patent applies partial action by performing only the necessary normalization steps rather than always executing full normalization. When bit overlap conditions are detected, the system performs limited normalization with rounding adjustments, achieving sufficient accuracy while reducing processing time and resolving the speed-accuracy contradiction.
3Reliability
If standard FMA operations are performed without optimization, then IEEE floating point standard compliance is ensured, but processing efficiency decreases
Solution Approach 1:
The patent introduces dynamics by making the FMA operation adaptive rather than static. The normalization process dynamically adjusts based on the detected relationship between addend and product bit patterns. This dynamic approach maintains IEEE compliance while improving processing efficiency by avoiding unnecessary computational steps in optimized cases.
4Measurement precision
If multiplication is performed with full precision, then accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent extracts and handles only the critical bits that affect the final result's accuracy. By focusing on the relationship between the addend's least significant bits and the product's most significant bits, the system performs multiplication with full precision where needed but avoids unnecessary full precision processing in cases where bit overlap allows for optimized handling, thereby reducing power consumption while maintaining accuracy.
Data Source
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AI summary
Improved processing in floating point fused multiply-add operations is described. An example of an apparatus includes a processor including circuitry to perform a floating point fused multiply-add (FMA) instruction, the FMA instruction requesting a calculation including multiplication of a first factor with a second factor to generate a product and addition of an addend to the product to generate a result; wherein, upon receiving the FMA instruction, the processor is to determine a shift to be applied in the calculation for the FMA instruction; determine whether a modified operation is applicable to the calculation for the FMA instruction, the determination being based at least in part on the determined shift to be applied in the calculation; and upon determining that the modified operation is applicable to the calculation for the FMA instruction, perform the modified operation to generate the result for the FMA instruction.