FMA Hardware Denormal Operand Processing Logic
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Solution Overview
Problem
Existing FMA designs face challenges in processing denormal numbers due to uncertainty in their true exponent value, leading to complications in alignment and accumulation, which results in increased latency and execution speed issues, as prior art methods like prenormalization introduce critical path delays.
Innovation Solution
A microprocessor method that determines the exponent difference and leading zeroes in denormal accumulator operands, allowing for conditional left-shifting and accumulation within a partial product adder, or deferring accumulation to a second stage based on specific conditions, to efficiently handle denormal inputs without prenormalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prenormalization is performed to handle denormal operands, then alignment accuracy is improved, but execution speed deteriorates due to critical path delays
Solution Approach 1:
The patent applies preliminary action by counting leading zeroes in the significand of denormal operands during the operand preparation stage, before the main FMA computation. This early determination of the number of leading zeroes allows the system to pre-calculate the appropriate shift amount, enabling accurate alignment of denormal operands with the partial product adder without introducing critical path delays during the main computation phase.
2Speed
If denormal operands are processed without prenormalization, then execution speed is improved, but alignment accuracy deteriorates due to unknown true exponent values
Solution Approach 1:
The patent applies parameter changes by using the number of leading zeroes in the significand as a substitute parameter for the unknown true exponent value of denormal operands. By counting the leading zeroes (which directly relates to the magnitude of the denormal number), the system can determine the appropriate alignment shift without needing to know or calculate the true exponent, thus maintaining both speed and alignment accuracy.
3Device complexity
If denormal accumulator operands are always accumulated separately, then alignment complexity is reduced, but productivity deteriorates due to additional latency
Solution Approach 1:
The patent applies dynamics by making the accumulation path dynamic based on the characteristics of the accumulator operand. The system dynamically determines whether to accumulate the denormal accumulator operand in the partial product adder or separately, based on the number of leading zeroes and the exponent difference. This dynamic decision-making allows the system to optimize for speed when possible (accumulating in partial product adder) while maintaining correctness when necessary (separate accumulation), thereby improving overall throughput without excessive complexity.
Data Source
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AI summary
A microprocessor includes FMA execution logic that determines whether to accumulate an accumulator operand C to the partial products of multiplier and multiplicand operands A and B in the partial product adder or in a second accumulation stage. The logic calculates an exponent delta of Aexp + Bexp - Cexp and determines the number of leading zeroes in C, if C is denormal. The microprocessor accumulates C with the partial products of A and B when the accumulation of C to the product of A and B could result in mass cancellation, when ExpDelta is greater than or equal to -K (where K is related to a width of a datapath in the partial product adder), and when a C isdenormal and its number of leading zeroes plus K exceeds-ExpDelta. The strategic use of resources in the partial product adder and second accumulation stage reduces latency.