Multi-path FMA Unit Power Control via Dynamic Path Selection
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Solution Overview
Problem
Floating-point circuitry in processors consumes substantial power due to the execution of fused multiply-add (FMA) operations, which are not efficiently managed in terms of power control and path utilization.
Innovation Solution
The implementation of a pipelined FMA unit with multiple paths and power control circuitry, where classification circuitry assigns operations to near-path or far-path circuitry based on operand exponents, allowing for shared circuitry and data gating to reduce dynamic power consumption by operating non-selected paths in a low-power mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple paths are implemented for FMA operations, then performance and precision are improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic path selection where classification circuitry determines whether to use near-path or far-path circuitry based on the specific FMA operation requirements. The system dynamically activates only the necessary circuitry path, avoiding the static power consumption of having all paths fully operational simultaneously. This dynamic approach maintains high performance when needed while reducing power consumption during normal operations.
Solution Approach 2:
The patent applies different quality levels to different circuitry paths based on operational needs. The near-path circuitry is optimized for common operations with lower precision requirements, while the far-path circuitry provides higher precision for specialized operations. This local differentiation allows the system to achieve high overall performance without all circuitry operating at maximum capability continuously, thereby reducing power consumption.
2Use of energy by moving object
If non-selected paths are operated in low-power mode, then power consumption is reduced, but switching time increases
Solution Approach 1:
The patent employs preliminary classification of FMA operations using classification circuitry that determines the appropriate execution path before computation begins. This preliminary action allows the system to pre-configure the selected path and keep non-selected paths in low-power mode without requiring time-consuming transitions during operation. The classification happens in advance, eliminating switching delays during actual FMA execution.
Solution Approach 2:
The patent implements periodic power management where non-selected paths are periodically switched to low-power mode between operations. The classification circuitry and control logic establish a rhythmic pattern of path selection and power state transitions, allowing the system to optimize power consumption without introducing unpredictable delays. This periodic approach creates predictable timing behavior while maintaining performance.
Data Source
AI summary
Techniques are disclosed relating to circuitry configured to perform floating-point operations such as fused multiply-addition (FMA) with multiple paths and power control. In some embodiments, an FMA unit includes a near path and multiple far paths and is configured to select a path based on a determined exponent difference. In some embodiments, the FMA unit is configured to operate portions of non-selected paths in a low power state.