Fused Multiply Add Floating Point Unit Interleaved Processing
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Solution Overview
Problem
Existing fused multiply add units in floating point processors suffer from reduced precision and increased processing time due to intermediate rounding steps and sequential execution of instructions, which can lead to inaccurate results and inefficiencies, especially when handling sequences of operations like dot products.
Innovation Solution
The proposed data processing apparatus includes separate multiplying and adding circuitry that operate in multiple processing cycles, allowing operand A to be input later than operands B and C, enabling interleaved processing of instructions and avoiding intermediate rounding, thus improving throughput and accuracy by generating an unrounded product that is added to operand A in a single final rounding step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If intermediate rounding is performed in sequential multiply-add operations, then processing can be done in discrete steps with simpler circuitry, but precision is reduced and accuracy deteriorates
Solution Approach 1:
The patent combines the multiply and add operations into a single fused operation that processes both operations simultaneously without intermediate rounding. The multiplying circuitry generates an unrounded product which is then directly added to the third operand in the same processing pipeline, eliminating the need for separate rounding steps and intermediate storage, thus maintaining full precision throughout the calculation.
Solution Approach 2:
The fused multiply-add unit maintains continuous processing by keeping the unrounded product in the data path and immediately feeding it into the adding circuitry without interruption or rounding. This continuous action preserves all significant bits from the multiplication through to the final addition result, avoiding precision loss that would occur with discrete rounding steps.
2Measurement precision
If fused multiply add operations are implemented with full precision, then accuracy is improved, but processing time increases and throughput decreases
Solution Approach 1:
The patent segments the fused multiply-add operation into distinct functional units: a multiplying circuitry that handles the B*C operation and generates unrounded products, and an adding circuitry that receives the unrounded product and operand A for the final addition. This segmentation allows each unit to be optimized independently while maintaining the continuous unrounded data path, improving overall throughput without sacrificing precision.
3Device complexity
If sequential processing is used for multiply and add operations, then circuit design is simpler, but processing time increases and efficiency decreases
Solution Approach 1:
The patent merges the multiply and add operations into a single fused instruction pipeline where both operations execute concurrently. The multiplying circuitry and adding circuitry are integrated in such a way that the multiply operation feeds directly into the add operation without requiring the sequential execution model, thereby reducing total processing time while maintaining manageable circuit complexity through systematic design.
Data Source
AI summary
A fused multiply add floating point unit 1 includes multiplying circuitry 4 and adding circuitry 8. The multiply circuitry 4 multiplies operands B and C having N-bit significands to generate an unrounded product B*C. The unrounded product B*C has an M-bit significand, where M>N. The adding circuitry 8 receives an operand A that is input at a later processing cycle than a processing cycle at which the multiplying circuitry 4 receives operands B and C. The adding circuitry 8 commences processing of the operand A after the unrounded product B*C is generated by the multiplying circuitry 4. The adding circuitry 8 adds the operand A to the unrounded product B*C and outputs a rounded result A+B*C.