FMA Low Functional Unit for Multi-Precision Floating-Point Efficiency
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Solution Overview
Problem
Conventional processors face inefficiencies in performing multi-precision floating-point operations, particularly in applications requiring high precision, as native floating-point precision is often insufficient, leading to increased execution time and hardware costs due to software emulation of FMA operations.
Innovation Solution
Implementing a hardware-based FMA low operation that computes the low part or tail of a FMA, reducing the number of floating-point operations required and maintaining accuracy by separating the result into high, low, and lowest FP values, thereby enhancing efficiency and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software emulation is used to perform multi-precision FMA operations, then precision requirements are met, but execution time increases and processing efficiency decreases
Solution Approach 1:
The patent segments the FMA operation into distinct functional units: a high-precision FMA unit for accurate computation and a low-precision FMA unit for efficient computation. By dividing the processing task between these specialized units, the system achieves both high precision and high efficiency simultaneously, resolving the contradiction between precision and productivity.
2Measurement precision
If conventional FMA operations are used, then native floating-point precision is maintained, but the number of operations increases for multi-precision computations
Solution Approach 1:
The patent applies partial action by using the low-precision FMA unit to compute only the necessary lower-precision result when full high-precision computation is not required. This allows the system to perform fewer operations while still meeting the precision requirements of the application, thereby reducing execution time and eliminating unnecessary computational overhead.
3Measurement precision
If high-precision FMA operations are performed using software emulation, then accuracy is maintained, but hardware resources and costs increase
Solution Approach 1:
The patent creates a universal FMA processing system that can handle both high-precision and low-precision operations through a single hardware architecture. The system includes both high-precision and low-precision FMA units that can be selectively used based on the specific computational requirements, eliminating the need for separate hardware systems and reducing overall device complexity while maintaining accuracy when needed.
Data Source
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AI summary
An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.