Fused Multiply Add Mantissa Adder 1's Complement Delay Reduction
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Solution Overview
Problem
Current fused multiply-add (FMA) operations in processors face inefficiencies due to delays in 1's complement operations and the separation of 2's complement and rounding processes, which affect the performance and precision of floating-point arithmetic.
Innovation Solution
The implementation of a mantissa adder with reduced 1's complement delay and the merging of 2's complement and rounding logic within the rounding unit to facilitate simultaneous 1's complement and rounding operations, utilizing pre-compute circuits to determine sign bits and control 1's complement logic, and optimizing the arithmetic right shift circuit to reduce delays across FMA operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional FMA operations are used with separate 2's complement and rounding processes, then the processing steps are clear and modular, but the operation delay increases and throughput decreases
Solution Approach 1:
The patent merges the 2's complement completion and rounding operations into a single integrated rounding unit. The rounding unit simultaneously performs 1's complement generation and rounding decision, eliminating the sequential execution delay between separate operations. This is achieved by sharing hardware resources and coordinating control signals to execute both functions in parallel within the same operational cycle.
Solution Approach 2:
The patent implements pre-compute circuits that determine sign bits and prepare control signals for the 1's complement logic before the actual addition operation completes. By anticipating the need for complement operations and preparing control signals in advance, the system reduces the critical path delay and enables faster execution of the FMA operation.
2Reliability
If 2's complement and rounding are performed as separate operations, then each operation can be optimized independently, but the overall operation delay increases
Solution Approach 1:
The patent combines the 2's complement completion logic and rounding logic into a single integrated rounding unit. This unified structure maintains functional clarity while reducing overall device complexity by eliminating redundant control paths and shared resources between separate operations. The integrated design preserves numerical precision while streamlining the hardware architecture.
3Productivity
If traditional adder circuits are used without optimized 1's complement logic, then the circuit design is simpler, but the complement operation delay reduces productivity
Solution Approach 1:
The patent implements pre-compute circuits that determine sign bits and prepare control signals for the 1's complement logic before the addition operation completes. This preliminary preparation of control signals enables the complement operation to execute in parallel with other FMA operations, significantly reducing the critical path delay without requiring complex reconfiguration of the adder circuitry.
Data Source
AI summary
A method includes receiving a carry-sum value corresponding to a first portion of inputs to an adder, and receiving a second value corresponding to a second portion of inputs to the adder that do not overlap the first portion. Method includes providing an intermediate sum of carry and sum values of the carry-sum value, which generates a carry out (Cout). Method includes determining a sign of incremented second value, and a sign of non-incremented second value; complementing or passing, responsive to sign of incremented result, the incremented result as a first output; complementing or passing, responsive to sign of non-incremented result, the non-incremented result as a second output; complementing or passing, responsive to Cout, sign of incremented result, and sign of non-incremented result, the intermediate sum as a third output; selecting one of the first, second outputs responsive to Cout; and providing final sum comprising third output and selected output.