Fused-Unfused FMA Module Single Opcode Rounding

Solution Overview

Problem

Conventional computer processors require additional pipeline stages to perform both fused and unfused multiply-add rounding operations, which increases complexity and resource utilization.

Innovation Solution

A single fused-unfused floating point multiply-add (FMA) module is implemented, capable of computing both fused and unfused multiply-add rounding results using a single opcode, with additional hardware that calculates unfused multiply-add rounding without adding pipeline stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional pipeline stages are added to perform both fused and unfused multiply-add rounding operations, then computational capability is improved, but device complexity increases

Engineering Contradiction:

Improvecomputational capabilityVSAvoidpipeline stages

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The FMA module is designed to perform both fused multiply-add rounding and unfused multiply-add rounding operations using a single unified structure. The module includes a carry save adder, full adders, carry lookahead adder, and rounding logic that can handle both rounding modes without requiring separate pipeline stages, thereby achieving multi-functionality while avoiding increased complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the fused and unfused multiply-add rounding operations into a single integrated FMA module. The carry save adder, full adders, and rounding logic are combined in one structure that processes both operation types simultaneously, eliminating the need for separate pipeline stages and reducing overall device complexity

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If additional pipeline stages are added to perform both fused and unfused multiply-add rounding operations, then computational capability is improved, but resource utilization increases

Engineering Contradiction:

Improvecomputational capabilityVSAvoidresource utilization

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The FMA module is designed to perform both fused multiply-add rounding and unfused multiply-add rounding operations using a single unified structure. The module includes a carry save adder, full adders, carry lookahead adder, and rounding logic that can handle both rounding modes without requiring separate pipeline stages, thereby achieving multi-functionality while avoiding increased complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the fused and unfused multiply-add rounding operations into a single integrated FMA module. The carry save adder, full adders, and rounding logic are combined in one structure that processes both operation types simultaneously, eliminating the need for separate pipeline stages and reducing overall device complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8990283B2Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module

Publication Date: 2015.03.24 ORACLE AMERICAN INC

AI summary

A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.