Fused Multiply Add Normalization Shift Error Correction
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Solution Overview
Problem
Conventional floating-point units with fused multiply add (FMA) units face normalization shift errors due to leading zero anticipator (LZA) and hardware optimization errors, leading to increased latency, power consumption, and area requirements, as well as errors in normalization shifts.
Innovation Solution
The design of a floating-point unit with a FMA hardware that corrects normalization shift errors using a single shift, pre-adjusting the mantissa and exponent to allow existing rounder logic to adjust for errors, reducing logic and delay, and employing a normalizer module, compensation logic, and a rounder to manage and correct shift errors in a data-dependent, low-latency manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware optimizations are introduced to reduce FMA unit latencies, then processing speed is improved, but normalization shift errors are introduced
Solution Approach 1:
The patent introduces a preliminary correction step that adjusts the normalization shift amount before the actual normalization operation. The correction logic predicts potential errors from LZA and hardware optimizations, then pre-adjusts the shift amount to compensate. This preliminary action ensures accurate normalization without requiring additional correction shifts, thus maintaining both speed and reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the correction logic monitors the FMA operation parameters (exponents of inputs A, B, C and their relationships) and adjusts the normalization shift amount accordingly. By detecting whether the product exponent exceeds the addend exponent (or vice versa), the system provides real-time correction to the normalization process, ensuring accuracy despite hardware optimizations.
2Speed
If LZA performs fast estimation of leading zeros in parallel with completion adder, then normalization speed is improved, but shift amount errors occur
Solution Approach 1:
The patent applies preliminary anti-action by introducing a correction logic that anticipates and counteracts the LZA estimation errors before they affect the normalization result. The correction logic determines when LZA may have overestimated or underestimated leading zeros based on exponent relationships, then pre-adjusts the normalization shift amount in the opposite direction of the expected error, canceling out the LZA inaccuracy.
Solution Approach 2:
The patent changes the normalization shift amount parameter dynamically based on detected error conditions. Instead of using the LZA estimate directly, the system modifies the shift amount by adding or subtracting correction values (typically ±1) based on exponent comparisons. This parameter adjustment transforms the potentially inaccurate LZA estimate into an accurate normalization shift value.
3Area of stationary object
If completion adder width and LZA width are limited to lower bits with incrementer for upper bits, then hardware area is reduced, but normalization errors are introduced
Solution Approach 1:
The patent introduces a correction logic as an intermediary between the truncated completion adder/LZA and the normalization unit. This intermediary component analyzes the exponent relationships and intermediate result characteristics to determine the appropriate correction to apply to the normalization shift amount. The correction logic acts as a mediator that compensates for the information loss from truncation without requiring full-width adders or LZA.
Solution Approach 2:
The patent adjusts the normalization shift amount parameter based on detection of truncation-induced errors. The correction logic monitors whether the truncated adder or LZA may have produced inaccurate leading zero counts due to width limitations, then modifies the shift amount accordingly. This parameter change compensates for the hardware optimization without requiring additional hardware resources.
Data Source
AI summary
A method for correcting a shift error in a fused multiply add operation. The method comprises adjusting a normalized floating-point number before performing a shift error correction to produce an adjusted normalized floating-point number, and correcting a shift error in the adjusted normalized floating-point number. The correcting the shift error comprises shifting a mantissa of the adjusted normalized floating-point number in one direction. A fused multiply add module comprising a normalizer module, a compensation logic, and a round. The normalizer module is operable to normalize a floating-point number to produce a normalized floating-point number. The floating-point number is normalized based upon an estimated quantity of leading zeros. The compensation logic is operable to manage a correction of a shift error in the normalized floating-point number. The rounder is operable to correct the shift error with a mantissa shift in only one direction.