Floating-Point Multiply-Add Unit with Operand Substitution Loading
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Solution Overview
Problem
Existing AI accelerators face inefficiencies due to infrastructure overhead, such as control complexity, wiring, and memory footprint, which reduce overall efficiency in performing floating-point operations, particularly in loading data to local register files, and require additional instructions and decode logic.
Innovation Solution
A processor-implemented method using a selectable-operation floating-point-multiply-add (soFMA) unit that eliminates the need for by-pass logic, second write ports, and dedicated load instructions by substituting operands with predefined values, allowing efficient loading of floating-point values through multiplexor circuitry and reducing hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated load instructions and decode logic are used to load floating-point values to local register files, then loading capability is provided, but hardware overhead (area, power, wiring complexity) increases
Solution Approach 1:
The multiply-add unit is designed to perform multiple functions: it can execute dedicated multiply-add instructions (A*B+C) and also function as a load store unit by substituting operands with predefined values (A=0, B=1, or C=1). This eliminates the need for separate dedicated load/store hardware infrastructure, reducing area, power, and wiring complexity while maintaining loading capability.
Solution Approach 2:
The patent merges the load/store functionality with the multiply-add unit by using operand substitution logic. The same computational unit handles both arithmetic operations and data loading, consolidating hardware resources and eliminating redundant infrastructure such as separate load decode logic and wiring.
2Productivity
If by-pass logic and second write ports are added to handle load operations, then loading efficiency improves, but device complexity and wiring complexity increase
Solution Approach 1:
The multiply-add unit serves dual purposes: performing arithmetic operations and executing load operations through operand substitution. By making the unit universal, the patent eliminates the need for additional by-pass logic and second write ports, thereby reducing wiring complexity while maintaining loading efficiency through the same computational pathway.
3Device complexity
If infrastructure overhead is reduced by eliminating dedicated load instructions, then area and power consumption decrease, but loading capability must be maintained
Solution Approach 1:
The multiply-add unit is enhanced to function as both an arithmetic unit and a load store unit. By substituting operands with predefined values (0 or 1), the unit can load floating-point values to local register files without requiring dedicated load instructions, thereby reducing area and power consumption while maintaining full loading capability.
Solution Approach 2:
The multiply-add unit performs loading operations autonomously by substituting its own operands with predefined values. This self-service capability eliminates the need for separate load infrastructure, allowing the unit to serve its own data loading needs without external dedicated hardware.
4Device complexity
If operand substitution with predefined values is used, then hardware overhead is reduced, but operation versatility must be maintained
Solution Approach 1:
The multiply-add unit achieves universality by combining arithmetic operations with load operations through operand substitution. The same unit can execute A*B+C instructions and load store operations, maintaining operation versatility while reducing hardware overhead by eliminating dedicated load/store infrastructure.
Solution Approach 2:
The patent changes the parameters of the multiply-add operation by substituting operands with predefined values (0 or 1). This parameter change transforms the operation from a pure arithmetic function to a dual-function unit that can also perform data loading, maintaining versatility while simplifying hardware.
Data Source
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AI summary
A processor is used for performing a floating-point multiply-add operation of a form A*B+C on at least one multiply-add unit, with three input floating-point operands A, B, C, wherein at least one of the operands A, B, C is substituted by at least one value of a predefined operand value set.