Fused Multiply Add Circuit Area Reduction via Segmented Addition
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Solution Overview
Problem
Existing floating point processors require significant area overhead for performing fused multiply add operations due to the need for wide adders and shifters, which is particularly problematic for smaller processors where circuit area is a concern.
Innovation Solution
The solution involves splitting the product of the multiplication into high and low order portions, allowing the fused multiply add operation to be performed using adders and shifters of similar width to those used for simple floating point addition, thereby reducing the circuit area required. This is achieved by adding the operand to one portion to generate an intermediate sum, which is then added to the remaining portion to produce the final result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wide adders and shifters are used to perform fused multiply add operations, then calculation precision is maintained, but circuit area overhead increases significantly
Solution Approach 1:
The patent segments the multiplication result into high-order and low-order portions, and performs addition in two separate steps. First, the operand A is added to one portion (e.g., high-order) to generate an intermediate sum. Then, the remaining portion (e.g., low-order) is added to the intermediate sum to produce the final result. This segmentation allows the use of narrower adders (similar width to operand A) instead of wide adders, significantly reducing circuit area while maintaining precision.
2Productivity
If the multiplication result is added in a single step using wide adders, then processing time is reduced, but circuit area overhead increases
Solution Approach 1:
The addition operation is segmented into two sequential steps instead of one single-step wide addition. The first step adds operand A to the high-order portion of the product, and the second step adds the low-order portion to the intermediate result. This time-for-area tradeoff uses two narrower adders sequentially, reducing circuit area at the expense of increased processing time, which is acceptable in many smaller processors where latency is not critical.
3Device complexity
If separate multiply and add operations are performed with rounding of intermediate results, then circuit complexity is reduced, but calculation precision deteriorates
Solution Approach 1:
The patent merges the multiply and add operations into a single fused operation without rounding the intermediate result. The multiplication of operands B and C is performed to generate a product, and this product is then added to operand A in a fused manner. By combining these operations and avoiding intermediate rounding, the patent maintains higher precision (equivalent to using wide adders) while using the segmented addition approach to reduce circuit area.
Data Source
AI summary
A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus 100 has multiplying circuitry 110 configured to multiply operands B and C to generate a product B*C having a high order portion 160 and a low order portion 170. The apparatus has adding circuitry 130 configured to: (i) add an operand A to one of the high order portion 160 and the low order portion 170 to generate an intermediate sum value; and (ii) add the intermediate sum value to a remaining one of the high order portion 160 and the low order portion 170 to generate a result A+B*C.