FMA Unit With Reduced Factor Bit Resolution
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Solution Overview
Problem
Existing FMA units in control units face challenges in achieving sufficient accuracy and efficiency due to high bit resolutions required for both factors and summands, leading to increased hardware complexity and reduced performance, especially when dealing with very small or large values.
Innovation Solution
The FMA unit operates with reduced accuracy for factors, using lower bit resolutions for multiplication while maintaining accuracy for the intermediate result, allowing for a 24 bits×24 bits integer multiplication and subsequent addition without internal conversion, thereby reducing hardware requirements and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high bit resolutions are used for both factors and summands in FMA unit, then computation accuracy is improved, but hardware complexity and chip space increase significantly
Solution Approach 1:
The patent applies different bit resolutions to different parts of the computation: factors use lower bit resolution (e.g., 24 bits) while the summand and final result use higher bit resolution (e.g., 64 bits). This local differentiation allows the multiplication operation to use reduced precision where sufficient, while maintaining high precision in the accumulation and final result where accuracy is critical, thereby reducing overall hardware complexity without sacrificing computation accuracy.
2Measurement precision
If high bit resolutions are used for factors and summands, then computation accuracy is improved, but hardware performance decreases due to increased logic requirements
Solution Approach 1:
The patent changes the bit resolution parameter for the factor inputs from high (64 bits) to lower (24 bits), while keeping the summand and output at high resolution (64 bits). This parameter change reduces the computational burden of the multiplication operation, allowing faster execution and improved hardware performance while maintaining sufficient accuracy through the high-precision summand and result representation.
3Measurement precision
If high bit resolutions are used for all inputs, then accuracy for very small or large values is maintained, but chip space increases noticeably
Solution Approach 1:
The patent applies high bit resolution locally only where it is most critical: in the summand input and the final output, which handle the accumulation and result representation including very small or large values. The factor inputs use lower bit resolution since their individual contribution to the final precision requirement is less critical. This localized high-precision approach maintains accuracy for extreme values while minimizing chip space consumption.
Data Source
AI summary
An FMA unit, for carrying out an arithmetic operation in a model computation unit of a control unit, is configured to process input of two factors and one summand in the form of floating point values, and provide a computation result of such processing as an output variable in the form of a floating point value. The FMA unit is designed to carry out a multiplication and a subsequent addition, the bit resolutions of the inputs for the factors being lower than the bit resolution of the input for the summand and the bit resolution of the output variable.