FMCW Chirp Bandwidth Control to Prevent Frequency Overshoot
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Solution Overview
Problem
Existing FMCW radar systems face accuracy issues due to frequency overshoot during transitions, which reduces data collection rates and radar system accuracy, and can cause the signal to exceed allocated bandwidth, leading to reduced performance.
Innovation Solution
A frequency modulated continuous wave (FMCW) synthesizer with a control engine, phase locked loop (PLL), frequency divider, control voltage generator, and voltage controlled oscillator (VCO) is used to generate chirp waveforms with controlled slope changes, avoiding overshoot by adjusting the filter bandwidth and charge pump current to ensure precise frequency transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the FMCW synthesizer directly changes frequency from F1 to F0 during idle time, then the transition speed is fast, but frequency overshoot occurs causing settling time increase
Solution Approach 1:
The patent applies preliminary action by introducing a ramp-down period before the idle time where the frequency is gradually reduced from F1 to F0. This preliminary frequency reduction prevents the direct discontinuous jump that causes overshoot, allowing the synthesizer to settle to F0 without extending the idle time significantly.
Solution Approach 2:
The patent makes the frequency transition dynamic by using different slopes for different phases: a steep negative slope during the ramp-down period for quick frequency reduction, and then a controlled transition during idle time. This dynamic approach optimizes both transition speed and settling behavior.
2Use of energy by moving object
If the FMCW radar system power amplifier is turned off during idle time, then power consumption is reduced, but additional resettling time is required in the receiver and synthesizer
Solution Approach 1:
The patent applies preliminary action by gradually reducing the frequency during the ramp-down period before turning off the power amplifier. This preliminary frequency adjustment allows the receiver and synthesizer to begin their settling process earlier, reducing the additional resettling time required after the amplifier is turned off.
3Reliability
If F0 and F1 are selected to keep overshoot within allocated bandwidth, then bandwidth compliance is maintained, but radar system accuracy is reduced due to reduced chirp bandwidth
Solution Approach 1:
The patent segments the frequency transition into multiple phases: a ramp-down period with negative slope, an idle time with zero slope, and then the next chirp with positive slope. This segmentation allows the frequency to return to F0 without overshooting beyond the allocated bandwidth, while maintaining the full chirp bandwidth for accurate radar measurements during the active chirp period.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables accurate and efficient generation of FMCW chirp waveforms, reducing idle time, increasing data collection rates, and maintaining signal quality within allocated bandwidth, thereby enhancing the accuracy and efficiency of FMCW radar systems.
Implementation Method 1
A frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO).
Implementation Method 2
The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage.
Implementation Method 3
Each chirp signal slews up or down in frequency over a fixed period of time. At time t1, the control signal 104 (F0, s1) instructs the FMCW synthesizer 108 to start at frequency F0, and to slew the output frequency 112 higher with slope s1, generating the FMCW chirp 108.
Data Source
AI summary
In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.