FMCW PLL Bandwidth Switching for Low Phase Noise and Fast Reset
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Solution Overview
Problem
FMCW PLL implementations face challenges in efficiently managing phase noise and reset time, which affect the dynamic range and power consumption of radar systems, due to the need for varying PLL bandwidth during acquisition and reset periods.
Innovation Solution
The system employs dynamic adjustment of PLL bandwidth using variable capacitance in low-pass filter circuitry, assisted by digital and analog converters for current injection, and charge pump circuitry to control the chirp timing, allowing for narrower bandwidth during acquisition and wider bandwidth during reset, thereby reducing phase noise and minimizing reset time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a higher PLL bandwidth is used during reset period to reduce reset time, then reset time is reduced, but phase noise increases during acquisition period
Solution Approach 1:
The patent implements dynamic adjustment of PLL bandwidth by switching between different capacitor values in the LPF circuit. During reset period, a smaller capacitor value provides higher bandwidth for fast settling. During acquisition period, a larger capacitor value provides lower bandwidth to reduce phase noise. This dynamic reconfiguration resolves the contradiction between fast reset and low phase noise.
Solution Approach 2:
The patent changes the bandwidth parameter of the PLL system by adjusting the capacitance value in the low-pass filter. The system switches between at least two different capacitance values to achieve different bandwidth settings appropriate for different operational phases (reset vs. acquisition), thereby optimizing both reset speed and phase noise performance.
2Object-affected harmful factors
If a narrower PLL bandwidth is used during acquisition period to reduce phase noise, then phase noise is reduced, but reset time increases
Solution Approach 1:
The system dynamically switches the LPF capacitance value based on the operational phase. During acquisition, a larger capacitor provides narrow bandwidth for low phase noise. During reset, the capacitor is switched to a smaller value for high bandwidth and fast settling. This dynamic adaptation resolves the trade-off between phase noise reduction and reset speed.
Solution Approach 2:
The bandwidth parameter is changed by switching capacitor values in the LPF circuit. The system uses at least two different capacitance settings: a larger capacitance during acquisition for narrow bandwidth and low phase noise, and a smaller capacitance during reset for wide bandwidth and fast reset time.
3Device complexity
If a fixed PLL bandwidth is used, then circuit complexity is reduced, but both phase noise and reset time cannot be optimized simultaneously
Solution Approach 1:
The LPF circuit is segmented into multiple capacitor branches that can be independently switched. Each capacitor branch corresponds to a specific bandwidth setting. The switching mechanism selects appropriate segments based on operational phase, enabling optimized performance without requiring a completely different circuit for each mode.
Solution Approach 2:
A single LPF circuit structure serves multiple functions by switching between different capacitance values. The same circuit hardware provides both narrow-bandwidth mode (for low phase noise during acquisition) and wide-bandwidth mode (for fast reset), eliminating the need for separate circuits and reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces phase noise during acquisition and shortens the reset time, enhancing the dynamic range and reducing power consumption of radar systems by optimizing PLL bandwidth settings.
Implementation Method 1
The variable BW being provided, in part, by variable capacitance circuitry in the low-pass filter (LPF) circuitry
Implementation Method 2
a digital and analog converter (DAC) for current injection to the LPF capacitors for pre-charging filter capacitance provided by the LPF capacitors
Implementation Method 3
charge pump (CP) circuitry
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.