FMCW Radar Baseband Processor Integration via Doppler Division Multiplexing
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Solution Overview
Problem
Current radar systems using frequency modulated continuous wave (FMCW) technology face inefficiencies in processing large volumes of data due to the requirement of storing the entire 3D radar cube before processing, which limits processing speed and memory efficiency.
Innovation Solution
The implementation of a method that processes individual horizontal 'slices' of the 3D radar cube in respective timeslots, allowing the Doppler FFT block to write only Range-Doppler coordinate pairs to memory, enabling pipelining and reducing memory requirements, and facilitating efficient target detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire 3D radar cube is stored before processing, then complete radar data is available for analysis, but memory requirements increase and processing speed decreases
Solution Approach 1:
The patent segments the 3D radar cube into individual horizontal slices (range bins) that can be processed independently in different timeslots. This segmentation allows processing to occur on smaller data units rather than requiring the entire cube in memory simultaneously, thus reducing memory requirements while maintaining data completeness for analysis.
Solution Approach 2:
The patent performs preliminary processing actions on individual range bins before complete cube assembly. By processing horizontal slices sequentially as they become available, the system prepares data incrementally rather than waiting for complete data accumulation, enabling earlier detection and reduced overall processing time.
2Reliability
If the entire 3D radar cube is stored before processing, then all radar data is available for comprehensive analysis, but processing time increases
Solution Approach 1:
The patent divides the processing task into segments corresponding to individual horizontal slices of the radar cube. Each slice can be processed independently and in parallel, allowing comprehensive analysis to proceed without waiting for complete data accumulation, thus reducing total processing time while maintaining analysis completeness.
Solution Approach 2:
The patent enables continuous processing by eliminating idle waiting time. As each horizontal slice is received, it is immediately processed without delay. This continuous useful action ensures that processing occurs as fast as data becomes available, maximizing throughput and reducing overall processing time while maintaining comprehensive analysis capability.
3Productivity
If individual horizontal slices are processed in timeslots, then memory requirements decrease and processing speed increases, but data integration complexity increases
Solution Approach 1:
The patent merges the results from individually processed horizontal slices to reconstruct the complete radar cube. By combining processed slice data in a systematic manner, the system achieves both fast individual processing and complete final analysis, balancing processing speed with data integration requirements.
Solution Approach 2:
The patent uses intermediate storage structures (such as buffers or temporary memory regions) to hold processed slice data before final integration. These intermediaries facilitate the combination of separately processed data segments, managing the complexity of data integration while enabling high-speed parallel processing of individual slices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces memory needs and enhances processing speed by allowing simultaneous processing of multiple range bins, enabling faster and more efficient detection of targets in radar systems.
Implementation Method 1
Doppler FFT block to write only Range-Doppler coordinate pairs to memory
Data Source
AI summary
Some aspects of the present disclosure relate to baseband processor for radar. The baseband processor includes a Doppler fast Fourier transform (FFT) circuit having an input and an output. An integration circuit has an input coupled to the output of the Doppler FFT circuit. A target detection circuit has an input coupled to an output of the integration circuit. The Doppler FFT circuit, the integration circuit, and the target detection circuit are each disposed on a silicon substrate, and the target detection circuit is arranged in series with the integration circuit and in series with the target detection circuit.