Fused Multiple Multiplication and Addition-Subtraction Instructions for Homomorphic Encryption
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Solution Overview
Problem
Polynomial multiplication and number-theoretic transform (NTT) operations in homomorphic encryption (HE) applications face performance bottlenecks, particularly due to the inefficiencies in polynomial modular multiplication and forward/inverse NTT computations.
Innovation Solution
The introduction of fused multiple multiplication and addition-subtraction (FMMAS) instructions, which allow for combined arithmetic operations on multiple inputs within a single processor instruction, optimizing polynomial arithmetic and accelerating NTT computations through hardware circuitry and instruction set enhancements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional separate multiplication and addition-subtraction instructions are used for polynomial arithmetic, then the instruction set is simple and easy to implement, but the computational overhead is high and performance is poor
Solution Approach 1:
The patent combines multiple multiplication operations and addition-subtraction operations into a single fused instruction (FMMAS). This merging of previously separate operations into one unified instruction reduces the total number of instructions needed for polynomial arithmetic and NTT operations, thereby reducing computational overhead and improving performance while managing hardware complexity through integrated circuit design.
Solution Approach 2:
The FMMAS instruction is designed to perform multiple functions: it can execute multiple multiplication operations and addition-subtraction operations within a single instruction cycle. This multi-functionality allows the same hardware circuitry to handle various polynomial arithmetic operations and NTT computations, improving productivity without proportionally increasing device complexity.
2Speed
If multiple separate instructions are used for multiplication and addition-subtraction operations, then the hardware implementation is simple, but the computational overhead increases and processing speed decreases
Solution Approach 1:
By merging multiple multiplication and addition-subtraction operations into a single FMMAS instruction, the patent reduces the number of instruction cycles required for polynomial arithmetic and NTT operations. This direct reduction in instruction count increases processing speed while the integrated hardware design manages the increased instructional complexity.
Solution Approach 2:
The FMMAS instruction performs multiple operations in a single fused execution cycle, effectively pre-combining operations that would otherwise require sequential execution. This preliminary fusion of operations eliminates the overhead of multiple separate instruction cycles, thereby increasing processing speed.
3Productivity
If fused multiple multiplication and addition-subtraction instructions are implemented, then computational overhead is reduced and performance improves, but the hardware circuitry and instruction set complexity increase
Solution Approach 1:
The patent implements the FMMAS instruction that merges multiple multiplication and addition-subtraction operations into a single unified operation. This merging reduces the total number of instructions executed in homomorphic encryption processes, improving productivity and efficiency while the integrated hardware design contains the complexity within a single instruction unit.
Solution Approach 2:
The FMMAS instruction provides multi-functionality by handling various polynomial arithmetic operations and NTT computations through a single instruction format. This universality improves the efficiency of homomorphic encryption processes without requiring separate dedicated hardware for each operation, thereby managing hardware complexity while enhancing productivity.
Data Source
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AI summary
An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused multiple multiplication and addition-subtraction operation, and execution circuitry to execute the decoded instruction according to the opcode to retrieve data from one or more locations indicated by the one or more source operands, to perform the fused multiple multiplication and addition-subtraction indicated by the opcode on four or more arguments indicated by the retrieved data to produce one or more results. Other embodiments are disclosed and claimed.