Fault Management Unit Prime String Selection
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Solution Overview
Problem
Current fault-tolerant computing systems in aerospace applications face challenges in efficiently managing and switching between redundant processing systems to maintain system reliability and availability, especially in remote environments where maintenance is not feasible.
Innovation Solution
The implementation of a Fault Management Unit (FMU) that builds a state representation of multiple processing systems, using Event Timer (ET) and String Handler (SH) circuitry to isolate faults and dynamically select the prime string based on consensus among ET circuitry, with features like Triple Mode Redundancy and Real Time Interrupt synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple redundant processing systems are used to achieve fault tolerance, then system reliability is improved, but device complexity increases due to the need for monitoring subsystems and voter mechanisms
Solution Approach 1:
The patent combines the fault detection and prime string selection functions into a unified state machine within the Fault Management Unit. Instead of separate voter mechanisms for each processing system, a single state machine evaluates the state of all processing systems and determines prime string assignment, reducing the number of monitoring subsystems and simplifying the overall architecture while maintaining fault tolerance capabilities
Solution Approach 2:
The state machine in the Fault Management Unit serves multiple functions: it monitors the state of multiple processing systems, detects faults, determines prime string assignment, and manages transitions between different system configurations. This multi-functional approach eliminates the need for dedicated voter mechanisms for each processing system, reducing device complexity while preserving reliability
2Difficulty of detecting and measuring
If voter mechanisms monitor each redundant system to detect faults, then fault detection capability is improved, but device complexity increases due to additional monitoring subsystems
Solution Approach 1:
The patent merges multiple voter functions into a single state machine that simultaneously monitors all processing systems. The state machine evaluates the state of each processing system and integrates this information to make unified fault detection and prime string selection decisions, eliminating the need for separate voter mechanisms and reducing device complexity while maintaining comprehensive fault detection capability
Solution Approach 2:
The state machine performs multiple monitoring and detection functions universally across all processing systems. It evaluates system state, detects faults, determines prime string assignment, and manages transitions, replacing multiple specialized voter mechanisms with a single multi-functional component that reduces overall system complexity
3Reliability
If the system switches between prime and online strings upon fault detection, then system availability is improved, but loss of time occurs during the switching process
Solution Approach 1:
The system performs preliminary actions by pre-evaluating the state of all processing systems and pre-determining the next prime string candidate before a fault occurs. The state machine continuously monitors system state and maintains readiness information, so when a fault is detected, the switch to an alternative prime string can occur with minimal delay as the candidate has already been identified and prepared
Solution Approach 2:
The patent implements dynamic state machine logic that adapts its behavior based on real-time system conditions. The state machine continuously evaluates system state and can dynamically transition between different operational modes, allowing for rapid and efficient prime string switching that minimizes downtime while maintaining system availability
Data Source
AI summary
Systems and methods for fault tolerant computing in accordance with various embodiments of the invention are disclosed. Fault tolerant computer systems in accordance with a number of embodiments of the invention include multiple processing systems supervised by a Fault Management Unit (FMU). The FMU can build a representation of the state of all of the multiple processing systems and then determines which of the processing systems to utilize to perform a particular function based upon this state representation.