Fowler-Nordheim Floating-Gate Synaptic Memory for Neuromorphic Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current analog memory technologies face challenges in implementing reliable and scalable synaptic memory for energy-efficient neuromorphic processors, with existing memristors exhibiting limited programming resolution, high device-to-device variability, and high energy requirements for programming and erasure, while also facing integration challenges with CMOS technology.
Innovation Solution
The development of an analog memory device utilizing Fowler-Nordheim tunneling with two nodes, each containing two floating gates connected by a capacitor, allowing for selective charge application to alter the energy barrier and enable quantum tunneling, which is used to create an adaptive synaptic array for dynamic analog memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memristors are used to implement synaptic memory, then the memory can be integrated into neuromorphic processors, but the programming resolution is limited and device-to-device variability is high
Solution Approach 1:
The memory device is divided into two separate nodes (first node for SET function, second node for RESET function), each with its own floating gates. This segmentation allows independent control and programming of each node, improving programming resolution and reducing the impact of device variability on overall system performance.
Solution Approach 2:
The patent utilizes Fowler-Nordheim tunneling to change the physical state of the floating gates by controlling charge injection parameters. By adjusting voltage, pulse duration, and tunneling conditions, precise control over the memory state is achieved, enabling high-resolution programming with minimal device variability.
2Duration of action of stationary object
If RRAM or MRAM are used to implement synaptic memory, then non-volatile storage is achieved, but integration with CMOS technology is challenging and fabrication costs increase
Solution Approach 1:
The patent employs floating-gate transistors that are compatible with standard CMOS technology while achieving non-volatile memory functionality. The same CMOS-compatible floating-gate structure used in FLASH memory is adapted for synaptic memory applications, enabling universal manufacturing processes and reducing fabrication complexity.
Solution Approach 2:
The patent replicates the successful floating-gate memory architecture from FLASH memory technology and adapts it for neuromorphic applications. By copying the proven CMOS-compatible structure and modifying it for analog weight storage, the patent achieves easy integration with existing CMOS manufacturing infrastructure.
3Ease of manufacture
If analog floating-gates are used to implement synaptic memory, then direct integration with CMOS neural circuitry is achieved, but high-voltage charge pumps are required for precision programming increasing energy requirements
Solution Approach 1:
The patent implements dynamic control of the floating gates through time-varying voltage pulses that enable Fowler-Nordheim tunneling. By dynamically adjusting the voltage magnitude and pulse duration, precise charge injection is achieved without requiring high-voltage charge pumps, reducing energy consumption while maintaining programming precision.
Solution Approach 2:
The patent changes the operational parameters from static high-voltage charging to dynamic low-voltage pulsed tunneling. By controlling the temporal characteristics of the voltage applied to the control gates, precise charge injection is achieved through quantum tunneling effects, eliminating the need for high-voltage charge pumps and significantly reducing energy consumption.
4Productivity
If memory elements are integrated in proximity with computing circuits to create compute-in-memory architecture, then the memory wall bottleneck is mitigated, but device complexity increases
Solution Approach 1:
The patent merges the memory function and computing function into a unified structure where floating-gate nodes serve both as storage elements for synaptic weights and as programmable elements for neural network operations. This merging eliminates the need for separate memory and processing units, reducing overall system complexity while enabling energy-efficient compute-in-memory operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a low-energy, scalable, and CMOS-compatible synaptic memory with high programming resolution and endurance, capable of synchronizing nodes with accuracy greater than 99.9% and retaining memory states for extended periods with minimal energy dissipation, effectively addressing the energy-efficiency bottleneck in machine learning processors.
Implementation Method 1
analog memory devices which utilize Fowler-Nordheim tunneling to provide an adaptive synaptic array for dynamic analog memory
Data Source
AI summary
An analog memory device includes a first node and a second node. The first node includes a first floating gate, a second floating gate, and a capacitor. The first node first floating gate is connected to the first node second floating gate via the capacitor. The second node includes a first floating gate, a second floating gate, and a capacitor. The second node first floating gate is connected to the second node second floating gate via the capacitor. The second node is connected to the first node, and an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time.