Fowler-Nordheim Memory Cell Structure for Low-Stress Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory devices face challenges with high manufacturing costs, complex design requirements, and limited data retention due to high voltages and currents needed for programming and erasing, which also restrict programming parallelism and lead to undesired erasing of memory cells.
Innovation Solution
A non-volatile memory device that uses the Fowler-Nordheim effect for both programming and erasing, with a memory cell structure that includes a first and second selection transistor and a floating gate storage transistor, allowing for reduced voltage and current requirements and improved data retention by minimizing electric stress on unselected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltages and currents are used for programming and erasing memory cells, then programming and erasing operations can be performed, but power consumption increases and data retention deteriorates due to electric stress on unselected memory cells
Solution Approach 1:
The patent applies local quality by making the electric field confinement selective: unselected memory cells are subjected to low electric field conditions through the off-state of selection transistors, while selected memory cells receive high electric field for programming/erasing. This spatial differentiation of electric field strength resolves the contradiction by enabling operations without subjecting all cells to high stress.
Solution Approach 2:
Selection transistors act as intermediaries that control the application of high voltages and currents. These transistors enable the desired programming/erasing operations on selected cells while blocking the harmful effects from propagating to unselected cells, thus resolving the contradiction between operational capability and data retention.
2Productivity
If high currents are used for programming memory cells, then programming operations can be performed quickly, but programming parallelism is limited due to current constraints
Solution Approach 1:
The patent segments the current path for each memory cell through individual selection transistors, allowing multiple cells to be programmed in parallel without current interference. This segmentation enables high programming speed for each cell while simultaneously supporting parallel operations across multiple cells, resolving the contradiction between speed and parallelism.
3Use of energy by moving object
If Fowler-Nordheim effect is used for programming and erasing, then voltage and current requirements are reduced, but complex charge pumps are still needed to generate required high voltages
Solution Approach 1:
The patent merges the programming and erasing operations into a unified Fowler-Nordheim effect mechanism, using the same physical principle for both operations by reversing the polarity of applied voltages. This consolidation reduces overall system complexity compared to using different mechanisms for programming and erasing, while still requiring charge pumps for high voltage generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, simplifies charge pumps, and increases programming parallelism while enhancing data retention, enabling the memory device to withstand a higher number of erasing operations without losing data.
Implementation Method 1
FTP memory device with programming and erasing based on Fowler-Nordheim effect
Implementation Method 2
the storage transistor has a distinct control gate region being capacitively coupled with its floating gate
Data Source
AI summary
An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are coupled in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.