Fo-eWLB Package Wire Bonding for Thickness Reduction
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Solution Overview
Problem
Current semiconductor packaging technologies face limitations in reducing the thickness of stacked semiconductor devices due to the thickness of substrates and flip chip interconnections, which constrains the height reduction of package profiles, especially in applications like smartphones.
Innovation Solution
The development of a wire bondable fan-out embedded wafer level ball grid array (Fo-eWLB) semiconductor package, which involves depositing an encapsulant over a semiconductor die, forming interconnect structures, and creating openings for wire bonding, allowing for direct electrical connections without the need for substrate bumps, thereby reducing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate and flip chip interconnections are used for electrical interconnection, then reliable electrical connection is achieved, but package thickness increases
Solution Approach 1:
The patent extracts and eliminates the substrate and flip chip interconnection structures from the packaging system. By using wire bonding directly from the semiconductor die to external contacts, the thick substrate and bump interconnections are removed, achieving reliable electrical connection without the thickness penalty of traditional substrate-based approaches.
Solution Approach 2:
The patent transitions from a planar substrate-based interconnection approach to a vertical wire bonding approach. By routing electrical connections through vertical openings in the encapsulant rather than through a thick substrate plane, the solution achieves reliable electrical connection while minimizing the horizontal footprint and overall package thickness.
2Reliability
If substrate bumps are used for electrical interconnection, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent removes the complex substrate bump formation process entirely from the manufacturing sequence. By using wire bonding instead of flip chip bump interconnection, the solution eliminates the need for precise bump alignment, bump formation, and substrate routing processes, significantly simplifying the manufacturing complexity while maintaining electrical interconnection reliability.
Solution Approach 2:
The patent replaces the mechanical flip chip bump interconnection system with an electrical wire bonding system. This substitution eliminates the need for mechanical alignment and physical contact between bumps and substrate pads, reducing manufacturing complexity through a more forgiving and established wire bonding process.
3Strength
If substrate is used for packaging, then structural support is provided, but package profile height increases
Solution Approach 1:
The patent extracts the structural support function from the thick substrate and relocates it to the encapsulant material and die mounting structure. By eliminating the substrate entirely and using the encapsulant to provide mechanical support and protection, the solution maintains structural integrity while achieving a significantly reduced package profile height.
Solution Approach 2:
The patent uses the encapsulant as a thin protective shell that provides both structural support and environmental protection. This thin-film approach replaces the thick rigid substrate, maintaining necessary mechanical strength while minimizing package height for applications like smartphones where profile is critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 15-20% reduction in package thickness and enables standardized manufacturing processes, reducing costs and improving thermal performance by eliminating the need for substrate bumps and allowing for more efficient electrical interconnections.
Implementation Method 1
depositing an encapsulant over the semiconductor die
Implementation Method 2
forming a bond wire in the opening in the first encapsulant
Data Source
AI summary
A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant. A modular interconnect structure including a conductive via is disposed adjacent to the first semiconductor die. The first encapsulant is deposited over the modular interconnect structure. An opening is formed in the first encapsulant extending to the modular interconnect structure or to the interconnect structure. A second semiconductor die is disposed over the first semiconductor die. A bond wire is formed over the second semiconductor die and extends into the opening in the first encapsulant. A cap is formed over an active region of the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and bond wire. Alternatively, a lid is formed over the second semiconductor die and bond wire.