Fo-WLCSP Recessed Interconnects for Thin Die Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fan-out wafer level chip scale packages (Fo-WLCSPs) with thin semiconductor dies are prone to damage during interconnect and handling, requiring specialized molds and increasing manufacturing costs, which affects production efficiency and unit production per hour (UPH) scheduling.
Innovation Solution
A method of forming recessed interconnect areas around the semiconductor die by creating recesses in a temporary layer or carrier, followed by encapsulation and the deposition of a conductive layer, which enhances the robustness of the Fo-WLCSP during interconnect processes and reduces the package profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If thin semiconductor die is used to reduce Fo-WLCSP profile, then package size is reduced, but susceptibility to damage during interconnect and handling increases
Solution Approach 1:
The patent applies beforehand cushioning by forming a recess in the encapsulant material before placing the thin semiconductor die. This recess creates a cushioning effect that absorbs mechanical stress and protects the thin die from damage during subsequent interconnect processes and handling, while still achieving the reduced package profile goal.
Solution Approach 2:
The patent introduces an intermediary structure - the recess formed in the encapsulant material - that mediates between the thin semiconductor die and external mechanical stresses. This recess acts as a buffer zone that protects the die without requiring specialized molds or additional handling procedures.
2Reliability
If specialized mold chase is used for thin semiconductor die encapsulation, then protection during interconnect is improved, but manufacturing cost increases and production efficiency decreases
Solution Approach 1:
The patent applies universality by creating a recess structure that can be formed using standard encapsulation processes without requiring specialized mold chases. This single recess structure serves multiple functions: protecting thin dies during interconnect, enabling standard handling procedures, and maintaining production efficiency with existing manufacturing equipment.
Solution Approach 2:
The patent uses the encapsulant material itself to form the protective recess structure, eliminating the need for expensive, specialized mold chases. This approach uses a readily available material (encapsulant) to provide protection that would otherwise require dedicated, costly tooling.
3Reliability
If recessed interconnect areas are formed by removing carrier and temporary layer, then robustness during interconnect is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the recess in the encapsulant material before placing the semiconductor die and completing the encapsulation process. This preliminary recess formation simplifies subsequent steps, as the protective structure is already in place before the die is mounted and interconnect is performed.
Solution Approach 2:
The patent merges the formation of the protective recess with the standard encapsulation process itself. Rather than adding a separate, complex process step to create protective structures, the recess is formed as an integral part of the encapsulation workflow, combining protection and packaging into a single unified process.
Data Source
AI summary
A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements.