Fo-WLCSP TSV and TMV Vertical Interconnect
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Solution Overview
Problem
Conventional fan-out wafer level chip scale packages (Fo-WLCSP) face challenges in achieving a fine interconnect pitch and vertical package integration due to limitations in z-direction electrical interconnect structures, which hinder miniaturization and increase package size.
Innovation Solution
A method involving the use of through-silicon vias (TSV) and through-mold vias (TMV) in Fo-WLCSP, where TSVs are formed in the semiconductor wafer and TMVs are created in the encapsulant, allowing for a fine pitch z-direction electrical interconnect and enabling vertical integration by forming an interconnect structure over the encapsulated assembly, facilitating package singulation and stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional z-direction electrical interconnect structures are used in Fo-WLCSP, then package integration is achieved, but interconnect pitch is coarse and package size increases
Solution Approach 1:
The patent transitions from planar x-y interconnect routing to three-dimensional z-direction interconnect routing using through-silicon vias (TSVs). This vertical dimension enables fine pitch interconnects by routing signals through the thickness of the substrate, achieving higher interconnect density without increasing package footprint.
Solution Approach 2:
The interconnect structure is segmented into multiple functional layers: through-silicon vias (TSVs) for vertical penetration, encapsulant material for isolation and support, and through-encapsulant vias (TEVs) for inter-package connectivity. This segmentation allows each component to be optimized independently, achieving fine pitch while maintaining package compactness.
2Manufacturing precision
If through-silicon vias and through-encapsulant vias are used, then fine pitch interconnect and vertical integration are achieved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of through-silicon vias and through-encapsulant vias into an integrated interconnect system. The TSVs provide intra-package vertical interconnect while TEVs provide inter-package connectivity, and both are formed using similar via-creation techniques, reducing overall manufacturing complexity despite the fine pitch requirements.
3Reliability
If bump interconnect is used for z-direction vertical interconnect, then electrical connection is achieved, but package stacking becomes difficult and delamination occurs
Solution Approach 1:
The patent extracts the interconnect function from traditional surface-mount bumps and relocates it to through-silicon via structures that penetrate the substrate vertically. This extraction eliminates the delamination risk associated with bumps while maintaining electrical connectivity, and the planar via openings enable reliable package stacking for three-dimensional integration.
Data Source
AI summary
A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.