Foggy-Fine Drain-Side Select Gate Reprogramming
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Solution Overview
Problem
The semi-circle drain side select gate (SC-SGD) memory technology faces challenges due to the exposure of the channel to neighboring electrical fields, leading to high upper tail issues in transistor threshold voltage distributions, which affect the reliability and efficiency of memory operations.
Innovation Solution
The implementation of drain-side select gate transistors with a control mechanism that programs the transistor threshold voltage using a foggy loop with increasing pulses by a first step amount followed by a fine loop with a second, smaller step amount, effectively addressing the high upper tail issue by fine-tuning the transistor threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semi-circle drain side select gate (SC-SGD) memory technology is used to reduce die size, then area efficiency is improved, but the channel becomes exposed to neighboring electrical fields causing high upper tail issues in transistor threshold voltage distributions
Solution Approach 1:
A control mechanism is introduced as an intermediary between the etching process and the final transistor structure. This control mechanism applies targeted voltage pulses during a foggy program operation to compensate for the electrical field exposure caused by the semi-circle geometry, thereby resolving the threshold voltage distribution issues while maintaining the area efficiency benefits
Solution Approach 2:
The invention changes the electrical parameters (voltage pulses with specific magnitudes and durations) applied to the drain-side select gate transistors during programming. By dynamically adjusting these parameters in a foggy program operation, the system compensates for the adverse effects of the semi-circle geometry on threshold voltage distribution while maintaining the compact die size
2Productivity
If etching technology is used to create semi-circular memory holes and separate blocks into strings, then manufacturing efficiency is improved, but portions of the drain-side select gate (such as metal shielding layers) are removed exposing the channel to neighboring electrical fields
Solution Approach 1:
The control mechanism performs preliminary compensation actions during the foggy program operation, applying voltage pulses before normal read/write operations. This preliminary action pre-corrects the threshold voltage shifts caused by the etching-induced exposure to neighboring electrical fields, allowing the etching process to proceed efficiently while mitigating its harmful effects
3Area of stationary object
If the metal shielding layer is removed to create semi-circular memory holes, then area efficiency is improved, but the channel becomes susceptible to neighboring electrical field interference
Solution Approach 1:
The control mechanism implements a feedback-based compensation strategy where voltage pulses are applied in a foggy program operation to counteract the electrical field interference. The system monitors and adjusts the threshold voltage of drain-side select gate transistors in response to the interference caused by removed shielding layers, maintaining reliable operation despite the area efficiency gains from semi-circular geometry
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.