Conductive Foil Interconnections for Power Semiconductor Modules
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Solution Overview
Problem
Conventional wire bonding methods for power semiconductor devices result in high parasitic inductance and resistance, leading to reliability issues and potential explosive failures due to electro-thermal-mechanical stress, especially at high switching frequencies.
Innovation Solution
The use of formed conductive foil elements, such as aluminum or copper foils with a thickness of 0.05 mm, to create electrical interconnections between power semiconductor devices and substrate modules, reducing inductance and resistance while increasing reliability by distributing current and heat more evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to interconnect power semiconductor devices to substrate modules, then electrical connections can be established, but parasitic inductance and resistance increase leading to reliability issues and potential explosive failures
Solution Approach 1:
The patent changes the fundamental geometric parameters of the interconnection structure by transitioning from wire bonding to foil-based connections. The foil elements provide larger contact surfaces and shorter current paths, fundamentally altering the electrical characteristics to reduce parasitic inductance and resistance while improving reliability
Solution Approach 2:
The invention transitions from one-dimensional wire connections to two-dimensional foil-based interconnections. The foil elements provide broader contact areas and distribute current across multiple dimensions, reducing current density and parasitic effects compared to traditional wire bonding
2Speed
If wire bonding is used for power IC interconnections, then electrical connections are made, but electro-thermal-mechanical stress causes failures at high switching frequencies
Solution Approach 1:
The patent modifies the physical parameters of the interconnection structure by using foil elements with larger surface areas and different geometries. This changes the thermal and mechanical stress distribution, allowing high switching frequencies to be achieved without the electro-thermal-mechanical stress failures that plague wire-bonded connections
3Object-generated harmful factors
If formed conductive foil elements are used to interconnect power semiconductor devices, then parasitic inductance and resistance are reduced, but the complexity of the interconnection structure increases
Solution Approach 1:
The foil-based interconnection elements serve multiple functions simultaneously: they provide electrical conduction, mechanical support, thermal management, and stress distribution. This multi-functionality reduces the need for separate components and simplifies the overall interconnection structure despite the advanced geometry
Solution Approach 2:
The invention merges the interconnection function with additional functions (thermal management, mechanical support) into a single integrated foil structure. This consolidation reduces the number of discrete components and simplifies the overall assembly process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces parasitic inductance and resistance, enhancing the reliability of power semiconductor device interconnections and preventing failures by minimizing thermal and mechanical stress, allowing for improved performance at higher switching frequencies.
Implementation Method 1
formed conductive foil elements, such as aluminum or copper foils with a thickness of 0.05 mm, to create electrical interconnections between power semiconductor devices and substrate modules, reducing inductance and resistance
Implementation Method 2
distributing current and heat more evenly... minimizing thermal and mechanical stress
Data Source
AI summary
An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1). A third foil element may be installed to electrically interconnect the discrete second device surfaces (B). The foil elements reduce interconnection parasitics and reduce charge and thermal energy density at device conductive surfaces as compared to wire bonded electrical interconnections. The foil elements may be comprised of formed metal elements that are flexible but sufficiently rigid to hold a formed shape or flexible foils supported on a flexible dielectric substrate.