Dynamically Foldable Instruction Fetch Pipeline for Latency Reduction
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Solution Overview
Problem
The lengthy instruction fetch process in processors is due to sequential access to memory structures, leading to high latency and performance issues, particularly exacerbated by long instruction fetch pipelines and branch mispredictions.
Innovation Solution
A dynamically-foldable instruction fetch pipeline that operates in parallel when in folded mode, utilizing a translation lookaside buffer (TLB), tag random access memory (RAM), and data RAM, allowing simultaneous access and reducing pipeline stages from 6 to 2, and dynamically unfolding when necessary to handle misses or mispredictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the instruction fetch process uses sequential access to memory structures (TLB, tag RAM, data RAM), then the pipeline stages can be extended to handle complex address translation and cache lookup, but the instruction fetch latency increases significantly
Solution Approach 1:
The patent performs address translation and cache tag comparison in parallel before the data RAM access is fully completed. By initiating these operations early and allowing them to proceed concurrently with the data retrieval, the system reduces the total instruction fetch latency while ensuring correct address translation and cache lookup results are obtained.
Solution Approach 2:
The patent dynamically adjusts the instruction fetch pipeline by selectively folding or unfolding pipeline stages based on whether a cache hit or miss occurs. This dynamic reconfiguration allows the pipeline to optimize between parallel execution (when cache hit is certain) and sequential execution (when cache miss requires further translation), thereby reducing average instruction fetch latency while maintaining reliability.
2Speed
If the instruction fetch pipeline is extended to handle complex address translation and cache lookup, then the processor can operate at higher clock frequencies, but the pipeline depth increases causing longer misprediction recovery time
Solution Approach 1:
The patent performs address translation and cache tag comparison operations in parallel with the instruction fetch pipeline, rather than sequentially. This preliminary parallel execution reduces the effective depth of the critical path, allowing the pipeline to be shorter while still handling complex address translation, thereby reducing misprediction recovery time while maintaining high clock frequency operation.
3Reliability
If all ways of the instruction cache data RAM are read out for every fetch request, then the correct instruction block can be reliably obtained even on cache hits, but power consumption increases
Solution Approach 1:
The patent performs cache tag comparison in parallel with the data RAM access to determine the correct way index before the data is fully read out. By having this determination ready in advance, the system can immediately select and output only the specific way containing the desired instruction block, rather than reading out all ways, thereby reducing power consumption while ensuring reliable instruction retrieval.
Data Source
AI summary
A dynamically-foldable instruction fetch pipeline receives a first fetch request that includes a fetch virtual address and includes first, second and third sub-pipelines that respectively include a translation lookaside buffer (TLB) that translates the fetch virtual address into a fetch physical address, a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache that receives a set index that selects a set of tag RAM tags for comparison with a tag portion of the fetch physical address to determine a correct way of the instruction cache, and a data RAM of the instruction cache that receives the set index and a way number that together specify a data RAM entry from which to fetch an instruction block. When a control signal indicates a folded mode, the sub-pipelines operate in a parallel manner. When the control signal indicates a unfolded mode, the sub-pipelines operate in a sequential manner.