Foldable Amorphous Wafer Integration for 3D Chip Packaging
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Solution Overview
Problem
Traditional semiconductor processes using crystalline materials are expensive due to the high cost of wafer production, where each chip requires additional supporting structures and is limited by the planar configuration, making it costly to manufacture and utilize.
Innovation Solution
The use of amorphous materials for semiconductor wafers that can be folded or formed into three-dimensional, non-planar configurations, allowing for the integration of multiple functional blocks including energy sources and other components, enabling cost-effective production and versatile device configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If crystalline semiconductor wafers are used for chip manufacturing, then the chips can be produced with standard processes, but the cost per chip is high due to expensive wafer production and requirement for additional supporting structures
Solution Approach 1:
The patent changes the material parameter from crystalline semiconductor to amorphous semiconductor, which fundamentally alters the manufacturing approach. Amorphous semiconductors can be deposited using lower-cost techniques such as sputtering or CVD rather than requiring expensive float-zone or Czochralski crystal growth processes, directly reducing wafer production cost
Solution Approach 2:
The patent transitions from traditional planar (2D) chip layouts to three-dimensional (3D) configurations by folding the wafer along defined fold lines. This dimensional change allows multiple functional blocks to be stacked vertically, increasing functional density without requiring additional supporting structures, thereby reducing cost per functional unit
2Ease of manufacture
If traditional planar wafer configuration is used, then manufacturing is straightforward, but the device functionality is limited and requires additional supporting structures
Solution Approach 1:
The patent introduces fold lines that enable the wafer to be transformed from a planar configuration to a three-dimensional folded structure. This allows the device to achieve complex spatial arrangements and integrated functionalities without requiring additional supporting structures, as the wafer itself forms the structural framework
Solution Approach 2:
The patent divides the wafer into multiple functional blocks separated by fold lines, allowing each block to be independently designed and positioned in three-dimensional space. This segmentation enables versatile device configurations while maintaining manufacturing simplicity through standardized wafer fabrication processes
3Productivity
If amorphous materials are used for semiconductor wafers, then the cost per chip is reduced and three-dimensional configurations are enabled, but the material properties differ from traditional crystalline semiconductors
Solution Approach 1:
The patent accepts the trade-off of using amorphous materials with different properties from crystalline semiconductors in exchange for significantly reduced manufacturing costs. The design compensates for material property differences through careful device architecture and folding configurations that optimize electrical and mechanical performance
Solution Approach 2:
The patent employs composite structures combining amorphous semiconductor layers with other materials deposited or formed on the wafer surfaces. These composite structures compensate for the limitations of amorphous materials while maintaining the cost advantages, achieving reliable device performance through material combinations rather than relying on a single material system
Data Source
AI summary
Semiconductor wafer devices are formed of a wafer or a portion of a wafer. The wafer or wafer portion includes a plurality of functional blocks, one of which comprises an energy source and another which takes some other form, such as digital logic, data storage, a communication module, a display, a display driver, or a sensor. A functional block may be formed as part of processing of the wafer or may comprise a post-processing element. The functional blocks combine to provide an operational system having a plurality of functions. The wafer may be formed of an amorphous material, allowing the device to have a three-dimensional, non-planar structure, such as a cuboidal or tubular structure. If the device comprises only a portion of a wafer, a plurality of devices may be formed from a single wafer, with each portion being removed from the remainder of the wafer to define a device.