Folded Active Inductor Loads for Faster High-Speed CML Switching
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Solution Overview
Problem
Current high-speed current mode logic (CML) circuits face challenges in achieving faster switching speeds due to parasitic and loading capacitances, with existing solutions like spiral inductors consuming excessive chip area and requiring additional high voltage generation circuitry, which complicates design and increases power consumption.
Innovation Solution
The implementation of folded active inductor loads in CML circuits, which absorb or offset parasitic and loading capacitances, enhancing rise/fall speed without the need for high voltage generation circuitry and reducing chip area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional spiral inductor shunt peaking is used to increase switching speeds, then switching speed is improved, but chip area consumption increases excessively
Solution Approach 1:
The patent replaces physical spiral inductors with an active inductor circuit implemented using transistors (specifically a PMOS transistor with specific biasing and configuration). This substitution eliminates the need for large-area passive inductor components while achieving the same shunt peaking effect for speed enhancement, directly resolving the contradiction between switching speed improvement and chip area consumption.
2Speed
If conventional active inductor shunt peaking is used to increase switching speeds, then switching speed is improved, but additional high voltage generation circuitry is required which increases design complexity
Solution Approach 1:
The patent modifies the operating parameters and configuration of the active inductor circuit to achieve shunt peaking effect using only the available supply voltage, eliminating the need for additional high voltage generation circuitry. By carefully selecting transistor sizes, biasing conditions, and circuit topology, the circuit achieves the desired speed enhancement while maintaining compatibility with standard voltage supplies, thus reducing design complexity.
3Speed
If conventional active inductor shunt peaking is used to increase switching speeds, then switching speed is improved, but additional high voltage generation circuitry is required which consumes chip area
Solution Approach 1:
The patent replaces the need for high voltage generation circuitry with a redesigned active inductor configuration that operates within the standard supply voltage range. This substitution eliminates the additional voltage generation blocks and their associated components, thereby reducing chip area consumption while maintaining the speed enhancement benefits of active inductor shunt peaking.
Data Source
AI summary
A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.