3D Microelectronic Packaging via Folded Board Joints
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Solution Overview
Problem
Conventional 3D microelectronic packaging technologies face issues such as poor reparability, thermal dissipation, signal interference, and long circuit wire paths, limiting their performance and reliability.
Innovation Solution
A microelectronic 3D packaging structure that uses a joint connection portion for physical and electrical bonding between adjacent boards, allowing for a folded structure with direct electrical connections and improved thermal management through a heat sink integration, enabling easier repair and reduced signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional 3D-stack chip packaging is used to integrate multiple chips, then the computation power and data processing speed are improved, but the reparability deteriorates because the whole package must be discarded when any chip fails
Solution Approach 1:
The packaging structure is divided into independent functional modules (first board with first electronic device, second board with second electronic device) connected through joint connection portions. This segmentation allows individual modules to be replaced or repaired without discarding the entire package, resolving the contradiction between high integration and reparability.
2Volume of moving object
If folding-up technique is used to form 3D structure, then the space utilization is improved, but the signal transmission speed deteriorates due to overly long circuit wire paths
Solution Approach 1:
The patent transitions from planar 2D layout to three-dimensional folded structure, utilizing vertical space to reduce wire path lengths. The folding connection portions enable direct electrical connections between adjacent board surfaces in 3D space, maintaining signal integrity while achieving compact packaging.
3Quantity of substance
If multiple electronic devices are closely mounted on top of each other in 3D structure, then the integration density is improved, but the signal integrity deteriorates due to significant interference between devices
Solution Approach 1:
The joint connection portions serve as intermediary elements between electronic devices on different boards, providing controlled electrical connections that minimize signal interference. The folding connection portions with folding lines create physical separation while maintaining electrical connectivity, acting as mediators that preserve signal integrity in high-density configurations.
4Quantity of substance
If conventional 3D-stack packaging is used to pack multiple chips, then the storage capacity is improved, but the thermal dissipation deteriorates
Solution Approach 1:
The package is segmented into multiple independent boards with joint connection portions, creating thermal pathways through the folding structures. This segmentation allows heat to dissipate through multiple surfaces and interfaces, improving thermal management while maintaining high integration density.
Data Source
AI summary
A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.