Folded Carrier IC Stack for Compact Packaging

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Solution Overview

Problem

Existing electronic device designs that package multiple integrated circuit dies face challenges in minimizing size and cost, as side-by-side mounting increases device width, wire-based coupling reduces electrical performance, and additional substrates increase expense and height.

Innovation Solution

A method involving mounting integrated circuit dies on a single carrier and folding it into layers to form a stack, using a flexible carrier material with conductive tracks and vias for electrical coupling, and embedding the carrier and dies in a moulded housing to minimize size and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If integrated circuit dies are mounted side by side on a substrate, then electrical coupling is achieved through conductive bumps, but the device width increases

Engineering Contradiction:
Improveelectrical couplingVSAvoiddevice width
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional side-by-side arrangement to a three-dimensional stacked arrangement by folding the substrate. Multiple integrated circuit dies are mounted on different portions of the substrate which is then folded to bring these portions into vertical alignment, creating a compact stack that reduces the device footprint while maintaining electrical coupling through conductive bumps and substrate traces.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of stationary object

If the second integrated circuit die is mounted on top of the first die using wires, then device width is reduced, but electrical performance deteriorates

Engineering Contradiction:
Improvedevice widthVSAvoidelectrical performance
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent extracts the electrical connection function from the traditional wire bonding approach and integrates it into the substrate structure itself. Conductive traces are formed within the substrate layers, providing direct electrical pathways between dies without requiring external wire bonds. This integration eliminates the performance degradation associated with long wire paths while maintaining the compact stacked architecture.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If an additional substrate is used to mount the second die, then electrical coupling is maintained, but manufacturing cost and device height increase

Engineering Contradiction:
Improveelectrical couplingVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the single substrate perform multiple functions: it serves as the mounting platform for both integrated circuit dies, provides electrical coupling pathways through its conductive traces, and acts as the structural framework that is folded to create the three-dimensional stack. This multi-functionality eliminates the need for additional substrates, reducing both manufacturing complexity and device height while maintaining reliable electrical connections.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2333831B1Method for packaging an electronic device
Publication Date: 2016.03.02 ST ERICSSON SA
  • EP2333831B1 patent drawingFigure 1
  • EP2333831B1 patent drawingFigure 2
  • EP2333831B1 patent drawingFigure 3

AI summary

An electronic device (100) comprises a plurality of integrated circuit dies (110, 120, 130) mounted on different areas of a carrier (150). The carrier (150) is folded into a plurality of layers, each layer comprising one of the different areas of the carrier (150) and one of the integrated circuit dies (110, 120, 130), such that the plurality of integrated circuit dies (110, 120, 130) form a stack. Adjacent surfaces of neighbouring layers are fixed together, for example by an adhesive layer (122, 132), and the folded carrier (150) and the integrated circuit dies (110, 120, 130) are embedded in a moulded material (180).