Folded Cascode Op-Amp Biasing for Low Noise and High Slew Rate
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Solution Overview
Problem
Folded cascode operational amplifiers face challenges in achieving low noise, low offset, and wide common mode input voltage range while maintaining high slew rates, as they require higher quiescent current to match slew rate performance with differential pair topologies, leading to increased noise and offset contributions.
Innovation Solution
The design incorporates a pair of input transistors with cascode transistors connected to controlled current sources, a bias circuit controlling these sources based on the emitter voltage of a second stage, and split compensation capacitors to maintain full slew rate performance with reduced quiescent current through the cascode stage, minimizing noise and offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the cascode transistors conduct the same amount of current as the input pair transistors to achieve comparable slew rate, then the slew rate performance is improved, but the quiescent current increases and the common mode input voltage range is substantially reduced
Solution Approach 1:
The patent implements dynamic current control in the cascode transistors through a bias circuit that adjusts the tail current of the second amplifier stage based on the common mode input voltage. This allows the cascode stage to operate with reduced quiescent current while maintaining adequate slew rate performance through dynamic current redistribution during signal transitions.
Solution Approach 2:
The patent changes the operating parameters of the cascode transistors by implementing separate biasing control that adjusts their current based on the common mode voltage level. This parameter adjustment allows the cascode stage to operate at optimized current levels that reduce quiescent power consumption while maintaining the required voltage swing capability for wide common mode input range.
2Measurement precision
If the quiescent current through the folded cascode transistors is reduced to minimize noise and offset, then the noise and offset contributions are reduced, but the slew rate is reduced
Solution Approach 1:
The bias circuit dynamically adjusts the current through the cascode transistors based on the operating conditions. During normal low-signal operation, the cascode current is reduced to minimize noise and offset contributions. During slewing conditions, the bias circuit increases the current to maintain adequate slew rate performance, thus resolving the contradiction between noise minimization and speed maintenance.
Solution Approach 2:
The patent employs periodic or transient current boosting through the bias circuit that activates during slewing conditions and reduces during normal operation. This time-varying current control allows the system to achieve low noise during steady-state operation while maintaining high slew rate when needed, effectively separating the noise-critical and speed-critical operating phases.
3Use of energy by moving object
If the load resistors R1 and R2 have high resistance to reduce current and improve common mode range, then the common mode input voltage range is improved, but the folded cascode stage transconductance Gm increases which increases noise and offset
Solution Approach 1:
The patent changes the transconductance parameter of the folded cascode stage by implementing dynamic biasing control. The bias circuit adjusts the operating point of the cascode transistors to maintain optimized transconductance values that prevent excessive noise and offset contributions even when operating with high-impedance load resistors for extended common mode range.
Data Source
AI summary
An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.