Folded Cascode Comparator Biasing for Fast Hysteresis Control
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Solution Overview
Problem
Comparator circuits face challenges in achieving high-speed operation while maintaining input accuracy and hysteresis generation, as existing methods introduce stray capacitance that increases propagation delay and require significant surface area, making it difficult to minimize input capacitance effectively.
Innovation Solution
A method for biasing the outputs of a folded cascode stage in a comparator using regulation and hysteresis currents flowing through resistive elements, controlled by cascode transistors, which compensates for differences in transistor threshold values and introduces a hysteresis offset without adding stray capacitance, thereby enhancing input-output speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional hysteresis structures with parallel transistor stacks are used, then hysteresis effect is achieved, but propagation delay increases due to stray capacitance
Solution Approach 1:
The patent extracts the hysteresis function from the conventional parallel transistor stack structure and relocates it to the output stage of the folded cascode amplifier. By using output transistors with different threshold voltages and appropriate biasing, the hysteresis effect is achieved without adding stray capacitance to the input nodes, thereby resolving the contradiction between reliability (hysteresis) and time loss (propagation delay).
Solution Approach 2:
The patent introduces an intermediary mechanism using the output transistors Q1 and Q2 of the folded cascode stage as mediators to generate hysteresis. These transistors, with deliberately different threshold voltages, create the hysteresis effect through their asymmetric conduction characteristics, eliminating the need for separate hysteresis circuitry that would otherwise increase propagation delay.
2Measurement precision
If resistive compensators are used to match transistor thresholds, then input accuracy is improved, but stray capacitance is introduced at transistor sources
Solution Approach 1:
The patent removes the resistive compensators from the transistor source nodes and relocates the threshold compensation function to the output stage. By using transistors with inherently different threshold voltages and appropriate current biasing, the compensation effect is achieved without introducing stray capacitance at the sensitive input nodes, thus resolving the contradiction between measurement precision and harmful stray capacitance.
3Measurement precision
If transistor pairs are manufactured with very close features, then comparison accuracy is improved, but manufacturing cost increases due to difficulty of matching
Solution Approach 1:
The patent deliberately introduces asymmetry by using transistors with different threshold voltages in the output stage (Q1 and Q2). This asymmetric design is intentionally created to generate hysteresis and simplify the overall circuit, avoiding the need for precise symmetric matching that would increase manufacturing difficulty and cost, while still achieving accurate comparison through the folded cascode topology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the input-output speed of the comparator while maintaining high accuracy and hysteresis generation, reducing propagation time by avoiding stray capacitance and allowing dynamic compensation of differential pair measurements.
Implementation Method 1
regulating the voltages on the positive output and on the negative output including a flow of a regulation current in two resistive elements that are situated respectively between the two outputs and a common-mode node
Implementation Method 2
A hysteresis current is generated in the two resistive elements in a manner controlled by a hysteresis control signal, so as to introduce a hysteresis offset to input values of the comparator
Data Source
AI summary
A comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.