3D Folded Cascode LNA for High Gain and Linearity
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Solution Overview
Problem
Ultra-low power cascode LNAs tend to exhibit either high gain or high linearity, but not both, which is a challenge in satellite-based applications like GPS and GNSS systems.
Innovation Solution
A cascode LNA structure incorporating a bipolar junction transistor (BJT) and a field effect transistor (FET) on different chips of a 3DIC, with a common-emitter amplifier in the input stage and a common-gate amplifier in the output stage, utilizing silicon germanium (SiGe) for the BJT and a P-channel FET, and passive devices in the interlayer dielectric and back end of the line metal levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If ultra-low power cascode LNA uses BJT-based amplifiers in each stage, then power consumption is reduced, but both gain and linearity cannot be achieved simultaneously
Solution Approach 1:
The LNA is divided into two separate stages: first stage uses BJT common-emitter amplifier for high gain, second stage uses FET common-gate amplifier for high linearity. This segmentation allows each stage to be optimized for its specific function, resolving the contradiction between gain and linearity while maintaining ultra-low power operation.
Solution Approach 2:
The patent transitions from a planar single-chip architecture to a three-dimensional stacked architecture using 3DIC technology. The BJT and FET are placed on different chips stacked vertically, enabling independent optimization of each transistor type without occupying the same physical space, thus achieving both high gain and high linearity simultaneously.
2Device complexity
If BJT and FET are integrated on the same chip, then device complexity is reduced, but performance optimization is limited
Solution Approach 1:
The patent employs three-dimensional integrated circuit (3DIC) technology to stack the BJT and FET on different chips vertically. This spatial reconfiguration reduces the electrical path length and parasitic effects between stages while allowing each transistor to be independently optimized for its specific function, thereby improving performance without significantly increasing overall device complexity.
Solution Approach 2:
A transformer is introduced as an intermediary component between the BJT first stage and FET second stage. This transformer provides impedance matching and signal coupling between the two differently-typed transistors, enabling optimal performance from both devices while they are integrated in the stacked architecture.
Data Source
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Figure 4A-1~4A-2
AI summary
A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E/C) regions and a base region between the E/C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S/D) regions, a channel region between the S/D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.