Class AB Folded Cascode Stage for Low-Noise High-Slew Op Amps
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Solution Overview
Problem
Folded cascode operational amplifiers face challenges in achieving low noise, low offset, and wide common mode input voltage range while maintaining high slew rates, as they require higher quiescent current to match slew rate performance with differential pair topologies, leading to increased noise and reduced common mode input voltage range.
Innovation Solution
A class AB folded cascode circuit with a differential current follower and current mirrors that reduce quiescent current through cascode transistors, allowing for lower noise and offset performance while maintaining high slew rates without signal distortion, by using bias voltage to control cascode transistor operation and converting differential output current to single-ended output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the cascode transistors conduct the same amount of current as the input pair transistors to achieve comparable slew rate, then the slew rate performance is improved, but the quiescent current increases and the common mode input voltage range is substantially reduced
Solution Approach 1:
The patent implements a dynamic current control mechanism where the cascode transistors operate in two distinct modes: during normal operation, they conduct reduced current to minimize quiescent current and noise; during slewing conditions, the current through cascode transistors is dynamically increased to match the input pair current, enabling high slew rate performance without continuously consuming high quiescent current
Solution Approach 2:
The invention changes the operating parameters of the cascode transistors by controlling their current conduction level. The cascode transistors switch between low-current mode (for low noise and low quiescent current) and high-current mode (for high slew rate), with the transition triggered by detection of slewing conditions through monitoring of differential input current
2Object-affected harmful factors
If the quiescent current through cascode transistors is reduced to minimize noise, then the noise contribution is reduced, but the slew rate deteriorates
Solution Approach 1:
The patent employs periodic or conditional action by activating high current mode only during slewing conditions rather than continuously. The circuit monitors for slewing conditions and dynamically adjusts cascode transistor current accordingly, enabling low noise during normal operation while providing high slew rate when needed
Solution Approach 2:
The cascode transistor current conduction is made dynamic rather than static, allowing the circuit to adapt between low-current operation (for low noise) and high-current operation (for high slew rate) based on real-time operating conditions
3Object-affected harmful factors
If the quiescent current through cascode transistors is reduced to minimize offset noise, then the offset contribution is reduced, but the slew rate performance deteriorates
Solution Approach 1:
The patent implements dynamic current control where cascode transistors operate at low quiescent current to minimize offset noise during normal operation, but can rapidly increase current during slewing conditions to maintain high slew rate performance, with the transition controlled by detection of large differential input current conditions
Data Source
AI summary
A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and second input conductors. An input of a first current mirror is coupled to the first input conductor, and an input of a second current mirror is coupled to the second input conductor. Outputs of the second and first current mirrors are coupled to collectors of the first and second cascode transistors, respectively, and also to first and second outputs, respectively, of the differential current follower. A third current mirror converts a differential output current in the first and second output conductors to a corresponding single-ended output voltage on the second output conductor.