Folded Channel Vertical Transistor Fabrication via Segmented Pillars
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Solution Overview
Problem
Conventional methods face challenges in fabricating vertical transistors with longer or variable gate lengths, as they require separate masks and are hindered by aspect ratio issues, making it difficult to achieve desired current on and off ratios for system-on-chip ICs.
Innovation Solution
The use of a dual depth shallow trench isolation process to form a folded channel path in gate all-around (GAA) vertical FETs, where pillar structures with a gate conductor surrounding them allow for adjustable channel lengths by varying the number of pillars, enabling longer or shorter gate lengths for different device requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional fabrication methods are used to fabricate vertical transistors with longer or variable gate lengths, then separate masks are required, but the process complexity and difficulty increase due to aspect ratio issues
Solution Approach 1:
The channel is segmented into multiple discrete pillar structures arranged in series, where each pillar represents a segment of the overall channel length. By varying the number of pillars, the total gate length can be adjusted without requiring separate masks for each length configuration, thus resolving the contradiction between achieving longer gate lengths and maintaining fabrication process simplicity.
2Reliability
If conventional fabrication methods are used, then standard channel lengths are achieved, but aspect ratio issues prevent achieving desired current on and off ratios
Solution Approach 1:
The channel structure transitions from a conventional planar configuration to a vertical three-dimensional architecture with pillars extending in the vertical dimension. This dimensional change allows the channel length to be effectively increased through vertical stacking rather than horizontal extension, improving current on and off ratios without suffering from the same aspect ratio constraints that limit conventional planar devices.
Data Source
AI summary
A semiconductor structure includes a substrate having a top surface, pillar structures formed on top of the substrate, a gate conductor, a drain/source region and a source/drain region. Each pillar structure of the pillar structures includes a first end and a second end, and the first end is closer to the substrate than the second end. The gate conductor surrounds each of the pillar structures disposed between the first end and the second end. The drain/source region is at the top surface of the substrate and in contact with the first end of a first pillar structure of the pillar structures, and the source/drain region is at the top surface of the substrate and in contact with the first end of a second pillar structure of the pillar structures.