Folded Parallel Chien Search for Lower-Logic BCH Decoding
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Solution Overview
Problem
Existing parallel Chien search architectures for BCH decoders require significant logic, which increases semiconductor costs, die size, and power consumption, particularly in mobile and handheld devices.
Innovation Solution
The implementation of a parallel Chien search with folding and a symbolized minimal polynomial combinational network (S-MPCN) that reduces logic usage by sharing paths and reusing logic, allowing for efficient examination of multiple roots in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel Chien search architectures are used to improve decoding efficiency, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple Chien search paths into a unified architecture where common logic is shared across parallel paths. The syndrome calculation and error location polynomial evaluation are merged into shared computational blocks that serve multiple search paths simultaneously, reducing overall logic complexity while maintaining parallel processing capability.
Solution Approach 2:
The patent creates universal computational blocks that can be reused across different parallel search paths. The syndrome calculator and polynomial evaluation logic are designed as multi-functional units that can process multiple error location scenarios, eliminating the need for dedicated logic for each parallel path.
2Productivity
If more logic is used in parallel Chien search, then decoding efficiency is improved, but power consumption increases
Solution Approach 1:
By merging common computational operations into shared logic blocks, the patent reduces the total number of active logic elements that consume power. The shared syndrome calculator and polynomial evaluation units are activated once to serve multiple parallel search paths, rather than having separate powered-up logic for each path.
Solution Approach 2:
The patent employs dynamic activation of parallel search paths based on actual decoding needs. Not all parallel paths are simultaneously active; instead, the architecture dynamically enables only the necessary paths, reducing overall power consumption while maintaining the capability for high-speed parallel processing when needed.
3Productivity
If more logic is used in parallel Chien search, then decoding efficiency is improved, but semiconductor die size increases
Solution Approach 1:
The patent merges redundant logic functions into shared computational blocks that are physically implemented once on the semiconductor die but logically serve multiple parallel search paths. This sharing approach dramatically reduces the total die area required compared to having separate dedicated logic for each parallel path.
Solution Approach 2:
The patent implements a nested architecture where universal computational blocks contain shared sub-functions that are reused across parallel paths. The syndrome calculator is nested within the polynomial evaluation logic, which in turn is shared across multiple search paths, creating a compact hierarchical structure that minimizes die area.
Data Source
AI summary
A hinge path is used to determine if a first possible root is a root of an error location polynomial. A positive limb path is used to determine if a second possible root is a root of the error location polynomial, including by using a sequence of coefficients associated with the error location polynomial. The sequence of coefficients is reversed and a negative limb path is used to determine if a third possible root is a root of the error location polynomial, including by using the reversed sequence of coefficients, wherein the negative limb path is a copy of the positive limb path.