Folded Clock Divider Architecture for Low-Power Multi-Ratio Clocks
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Solution Overview
Problem
Existing clock signal generation methods in electronic devices, such as systems on a chip, face high power consumption due to the use of multiple divider circuits for generating clock signals of different frequencies and duty cycles.
Innovation Solution
A method involving a clock divider counter that loads most significant bits of a divider value, decrements at each clock signal pulse, and generates a divided clock signal based on a toggle signal and reference values, allowing for efficient division by integer and fractional numbers while managing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple divider circuits are coupled to the phase locked loop output, then multiple clock signals of different frequencies can be generated, but power consumption increases undesirably
Solution Approach 1:
The patent merges multiple divider circuits into a single reconfigurable divider circuit that can perform multiple division operations sequentially. The single divider circuit is coupled to the phase locked loop output and can be reconfigured via control signals to provide different division ratios (e.g., divide by 2, 4, 8, 16), thereby generating multiple clock signals without requiring multiple simultaneous divider circuits, thus reducing power consumption while maintaining the ability to generate multiple clock frequencies.
Solution Approach 2:
The reconfigurable divider circuit is designed to perform multiple functions that would traditionally require separate dedicated circuits. By incorporating control logic and reconfigurable division logic, a single divider circuit can adapt to provide different clock division ratios as needed by different components in the system, making it a universal solution that replaces multiple specialized divider circuits and reduces overall power consumption.
2Use of energy by moving object
If a single reconfigurable divider circuit is used instead of multiple divider circuits, then power consumption is reduced, but the complexity of controlling the divider increases
Solution Approach 1:
The divider circuit incorporates dynamic reconfiguration capability where the division ratio can be changed on-the-fly based on system requirements. Control logic receives requests from different components for specific clock frequencies and dynamically adjusts the divider ratio accordingly. This dynamic approach allows a single circuit to adapt to varying needs without requiring permanent complex control structures for every possible division ratio, balancing flexibility with manageable complexity.
Data Source
AI summary
A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.