Folded Clock Divider Architecture for Low-Power Multi-Ratio Clocks
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Solution Overview
Problem
Existing clock signal generation methods in electronic devices, such as systems on a chip, face high power consumption due to the use of multiple divider circuits for generating clock signals of different frequencies and duty cycles.
Innovation Solution
A circuit comprising a counter circuit and a logic circuit that loads the most significant bits of a divider value, decrements at each clock pulse edge, and generates end count signals to reload the counter and toggle signals, allowing for efficient division of clock signals by integer and fractional numbers while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple divider circuits are coupled to the phase locked loop output, then multiple clock signals of different frequencies can be generated, but power consumption increases undesirably
Solution Approach 1:
The patent combines multiple divider functions into a single shared divider circuit. Instead of having separate divider circuits for divide-by-2, divide-by-4, and divide-by-8 operations, one divider circuit is reused multiple times with different division ratios. This merging eliminates redundant circuitry and reduces overall power consumption while maintaining the ability to generate multiple clock signals at different frequencies.
Solution Approach 2:
The divider circuit is designed to be universal and reconfigurable, capable of performing multiple division operations (divide-by-2, divide-by-4, divide-by-8, etc.) through a single circuit instance. The circuit can be programmed or configured to achieve different division ratios, making it multi-functional. This universality allows one circuit to replace what would traditionally require multiple dedicated circuits, thereby reducing power consumption.
2Adaptability or versatility
If multiple divider circuits are used for clock signal division, then various clock frequencies are available for different components, but device complexity increases
Solution Approach 1:
The patent merges multiple divider circuits into a single shared divider circuit that can be configured to perform different division operations. By combining the functionality of what would traditionally be separate circuits into one reconfigurable unit, the overall device complexity is reduced in terms of component count, while the adaptability to generate various clock frequencies is preserved through configuration options.
Solution Approach 2:
The divider circuit incorporates dynamic reconfiguration capability, allowing it to change its division ratio based on system requirements. This dynamic property enables a single circuit to adapt to different operating conditions and generate different clock frequencies as needed, replacing what would otherwise require multiple static divider circuits with fixed division ratios.
Data Source
AI summary
A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.