Folded CRC Circuit for Faster Image Data Error Checking

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Solution Overview

Problem

Existing data communication systems face challenges in optimizing CRC processing speed and efficiency, particularly in image processing systems, leading to increased complexity, area, and power consumption, while maintaining effective error detection and correction.

Innovation Solution

A CRC system and method utilizing data folding processing circuits and CRC processing circuits, including bit fold and stream fold operations, to optimize CRC operations, reduce complexity, and improve efficiency in image signal processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional CRC processing is used in image processing systems, then error detection capability is maintained, but processing speed is slow and complexity increases

Engineering Contradiction:
ImproveCRC processing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the input data into multiple segments (first data, second data, third data, etc.) and processes them through separate bit fold circuits simultaneously. This segmentation enables parallel processing, significantly improving CRC processing speed while maintaining manageable complexity through modular circuit design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a bit folding dimension that maps multiple data bits into fewer bits through fold circuits. By transforming the data representation dimension (from wide parallel bits to compressed folded bits), the system achieves faster processing with reduced computational complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If conventional CRC processing is used, then error detection is achieved, but area consumption increases

Engineering Contradiction:
Improveerror detection rateVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple data streams through bit fold circuits that combine several input data segments into folded data. This merging approach allows the system to maintain high error detection capability through comprehensive data coverage while reducing the area required by sharing common CRC processing resources

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The CRC processing circuit is designed to handle multiple folded data streams through a universal processing path. The same CRC logic unit processes different folded data segments, making the circuit multi-functional and reducing overall chip area compared to having separate CRC units for each data stream

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If conventional CRC processing is used, then error detection is maintained, but power consumption increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent implements continuous CRC processing by maintaining active bit fold circuits and CRC processing units that operate continuously on folded data streams. This continuous operation improves power efficiency by keeping circuits in optimal operating states rather than repeatedly activating and deactivating, while the folded data structure reduces the total number of operations required

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent changes the data representation parameters through bit folding, transforming wide data words into compressed folded representations. This parameter transformation reduces the number of processing steps and logic operations required for CRC calculation, directly lowering power consumption while maintaining error detection capability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4432090B1Cyclic redundancy check system and cyclic redundancy check method
Publication Date: 2025.10.15 SAMSUNG ELECTRONICS CO LTD
  • EP4432090B1 patent drawingFigure 1
  • EP4432090B1 patent drawingFigure 2
  • EP4432090B1 patent drawingFigure 3

AI summary

A cyclic redundancy check (CRC) system and a CRC method are provided. The CRC system includes a data folding processing circuit and a CRC processing circuit. The data folding processing circuit includes a first bit fold circuit configured to fold first input data into first fold data, a second bit fold circuit configured to fold second input data into second fold data, and a stream fold circuit configured to generate first fold streaming data based on the first fold data and the second fold data. The CRC processing circuit includes a first flip-flop configured to receive and store first dividend data of a first cycle, a second flip-flop configured to receive and store the first fold streaming data of the first cycle, and a CRC logic configured to perform a CRC operation on the first dividend data and the first fold streaming data.