Interleaved Folded Current-Steering DAC for High Sampling Rates

The patent divides the DAC driver into multiple independent folded driver circuits that operate in an interleaved manner. Each driver handles a portion of the sampling rate, allowing parallel operation that achieves high overall sampling rates while each individual driver consumes less power than a single high-speed driver would require.

The patent employs periodic switching between multiple folded drivers using clock signals. The drivers operate in alternating phases, with each driver active during specific time intervals. This periodic action distributes the power consumption over time and enables high effective sampling rates through interleaved operation.

The patent segments the high-speed DAC operation into multiple lower-speed folded drivers operating in parallel. Each driver requires less supply headroom than a single high-speed driver would need, and the interleaved operation maintains continuous high sampling rate while keeping individual driver headroom requirements manageable.

The patent uses dynamic switching between multiple folded drivers through clock-controlled switches. This dynamic allocation allows the system to maintain high effective sampling rates while each individual driver operates within safe headroom limits, adapting the active drivers based on timing requirements.

The patent divides the DAC into multiple folded driver circuits with separate current paths. This segmentation reduces the current stress on any single dielectric interface, thereby reducing the cumulative effect that leads to time-dependent dielectric breakdown while maintaining overall system functionality.

The patent introduces clock-controlled switching circuits as intermediaries that distribute current flow across multiple paths. These switching intermediaries prevent excessive current concentration at any single dielectric interface, reducing breakdown risk while maintaining design manageability through systematic control.