Folded Digit Line Architecture for DRAM Noise Cancellation
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Solution Overview
Problem
Integrated circuit designers face challenges in reducing feature sizes and increasing integration density of DRAM cells while maintaining performance, as smaller sizes lead to increased pattern noise and decreased electrical performance due to reduced separation distances between memory elements and connecting lines.
Innovation Solution
The implementation of a folded digit line architecture in DRAM memory arrays, where each pair of complimentary digit lines is coupled to alternate memory cells, and the use of finFETs with vertical fin structures to enhance control and reduce array size, along with specific trench and isolation trench designs to minimize noise and improve signal-to-noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes and separation distances are reduced to increase integration density, then integration density is improved, but pattern noise increases and electrical performance decreases
Solution Approach 1:
The memory array is divided into multiple blocks with folded digit lines, where each block has its own pair of digit lines. This segmentation isolates noise within each block, preventing noise propagation across the entire array, thereby maintaining electrical performance while achieving high integration density.
Solution Approach 2:
The folded digit line architecture converts the harmful effect of reduced separation distances (which increase noise) into a benefit by using the same digit lines to serve multiple memory cell blocks. This reuse of digit lines reduces the total number of digit lines needed, increasing integration density while the folded configuration maintains noise isolation.
2Quantity of substance
If feature sizes are reduced to increase integration density, then integration density is improved, but electrical performance decreases
Solution Approach 1:
The memory array is segmented into multiple blocks, each accessed through dedicated digit line pairs. This segmentation maintains electrical performance by limiting the impact of scaling effects to smaller, manageable blocks, while the overall array achieves high integration density through the folded architecture that efficiently packs these blocks.
Solution Approach 2:
The folded digit line architecture introduces a dimensional change by routing digit lines in a folded pattern rather than a simple linear array. This allows the memory array to achieve higher integration density by utilizing both horizontal and vertical spacing efficiently, while maintaining adequate separation distances for electrical performance through the folded configuration.
3Device complexity
If traditional open architecture is used, then design is simpler, but noise cancellation capability is insufficient
Solution Approach 1:
The folded digit line architecture converts the complexity of noise cancellation requirements into a benefit by using the folded configuration itself to provide noise cancellation. The paired digit lines in the folded architecture naturally cancel differential noise signals, eliminating the need for additional complex noise cancellation circuits while maintaining architectural simplicity.
Data Source
AI summary
Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.