Folded Digit Line Configurations for Memory Integration
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Solution Overview
Problem
Highly integrated memory arrays face issues with excessive noise due to undesired capacitive coupling between closely-spaced digit lines, which becomes more problematic with increasing levels of integration, and existing solutions often require shielding to mitigate this issue.
Innovation Solution
The implementation of vertically-stacked integrated assemblies with folded-digit-line-configurations that eliminate capacitive coupling without the need for shielding, allowing for tighter packing of digit lines and simplifying fabrication by removing the requirement for shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digit lines are closely spaced to increase integration density, then productivity is improved, but capacitive coupling between digit lines increases causing excessive noise
Solution Approach 1:
The patent transitions from planar digit line arrangements to three-dimensional folded configurations where digit lines are routed through multiple vertical levels. This dimensional change allows digit lines to be closely spaced in the plane while maintaining physical separation through vertical displacement, thereby increasing integration density without excessive capacitive coupling noise
Solution Approach 2:
The digit lines are segmented into multiple sections that are folded and routed through different vertical levels. This segmentation breaks the continuous planar path into discrete segments that can be spatially separated, reducing capacitive coupling while maintaining signal integrity for high-density integration
2Object-affected harmful factors
If shielding is added to reduce capacitive coupling noise, then noise reduction is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent extracts and eliminates the need for shielding structures by fundamentally redesigning the digit line geometry. Instead of adding shielding to suppress capacitive coupling, the folded digit line configuration inherently minimizes coupling through its three-dimensional routing, simplifying device complexity while maintaining noise reduction
3Object-affected harmful factors
If shielding is added to mitigate capacitive coupling, then noise reduction is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent removes the shielding component entirely from the manufacturing process. The folded digit line configuration achieves noise mitigation through its geometric design alone, eliminating the need for additional shielding fabrication steps and simplifying the overall manufacturing process
Data Source
AI summary
Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.